ltc4269cdkd-2 Linear Technology Corporation, ltc4269cdkd-2 Datasheet - Page 22

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ltc4269cdkd-2

Manufacturer Part Number
ltc4269cdkd-2
Description
Ieee 802.3at High Power Pd And Synchronous Forward Controller With Aux Support
Manufacturer
Linear Technology Corporation
Datasheet

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LTC4269-2
APPLICATIONS INFORMATION
maximum duty cycle clamp, the SS_MAXDC pin voltage
is programmed by a resistor divider from the 2.5V V
pin to GND. An increase of programmed voltage on
SS_MAXDC pin provides an increase of switch maximum
duty cycle clamp.
Soft-Start
The LTC4269-2 provides true PWM soft-start by using the
SS_MAXDC pin to control soft-start timing. The propor-
tional relationship between SS_MAXDC voltage and switch
maximum duty cycle clamp allows the SS_MAXDC pin
to slowly ramp output voltage by ramping the maximum
switch duty cycle clamp—until switch duty cycle clamp
seamlessly meets the natural duty cycle of the converter.
A soft-start event is triggered whenever V
SD_V
overcurrent threshold at OC pin is exceeded. Whenever a
soft-start event is triggered, switching at SOUT and OUT
is stopped immediately.
The SS_MAXDC pin is discharged and only released for
charging when it has fallen below its reset threshold
of 0.45V and all faults have been removed. Increasing
voltage on the SS_MAXDC pin above 0.8V will increase
switch maximum duty cycle. A capacitor to GND on the
SS_MAXDC pin in combination with a resistor divider from
V
Current Mode Topology (I
The LTC4269-2 current mode topology eases frequency
compensation requirements because the output inductor
does not contribute to phase delay in the regulator loop.
This current mode technique means that the error ampli-
fi er (nonisolated applications) or the optocoupler (isolated
applications) commands current (rather than voltage) to be
delivered to the output. This makes frequency compensa-
tion easier and provides faster loop response to output
load transients.
A resistor divider from the application’s output voltage gen-
erates a voltage at the inverting FB input of the LTC4269-2
error amplifi er (or to the input of an external optocoupler)
and is compared to an accurate reference (1.23V for
LTC4269-2). The error amplifi er output (COMP) defi nes the
input threshold (I
22
REF
, defi nes the soft-start timing.
SEC
is too low (power supply UVLO), or a 107mV
SENSE
) of the current sense comparator.
SENSE
Pin)
IN
is too low,
REF
COMP voltages between 0.8V (active threshold) and 2.5V
defi ne a maximum I
By connecting I
source of an external power MOSFET, the MOSFET peak
current trip point (turn off) can be controlled by COMP
level and hence by the output voltage. An increase in output
load current causing the output voltage to fall, will cause
COMP to rise, increasing I
current delivered to the output. For isolated applications,
the error amplifi er COMP output can be disabled to allow
the optocoupler to take control. Setting FB = V
the error amplifi er COMP output, reducing pin current to
(COMP – 0.7)/40k.
Slope Compensation
The current mode architecture requires slope compensation
to be added to the current sensing loop to prevent subhar-
monic oscillations which can occur for duty cycles above
50%. Unlike most current mode converters which have a
slope compensation ramp that is fi xed internally, placing a
constraint on inductor value and operating frequency, the
LTC4269-2 has externally adjustable slope compensation.
Slope compensation can be programmed by inserting an
external resistor (R
LTC4269-2 has a linear slope compensation ramp which
sources current out of the I
at 0% duty cycle to 35μA at 80% duty cycle.
Overcurrent Detection and Soft-Start (OC Pin)
An added feature to the LTC4269-2 is a precise 107mV
sense threshold at the OC pin used to detect overcurrent
conditions in the converter and set a soft-start latch. The
OC pin is connected directly to the source of the primary-
side MOSFET to monitor peak current in the MOSFET (Fig-
ure 13). The 107mV threshold is constant over the entire
duty cycle range of the converter because it is unaffected
by the slope compensation added to the I
Synchronizing
A SYNC pin allows the LTC4269-2 oscillator to be synchro-
nized to an external clock. The SYNC pin can be driven
from a logic-level output, requiring less than 0.8V for a
logic-level low and greater than 2.2V for a logic-level high.
Duty cycle should run between 10% and 90%. To avoid
SENSE
SLOPE
SENSE
to a sense resistor in series with the
) in series with the I
threshold from 0mV to 220mV.
SENSE
SENSE
threshold, increasing the
pin of approximately 8μA
SENSE
SENSE
REF
pin.
disables
pin. The
42692f

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