ltc4269cdkd-2 Linear Technology Corporation, ltc4269cdkd-2 Datasheet - Page 24

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ltc4269cdkd-2

Manufacturer Part Number
ltc4269cdkd-2
Description
Ieee 802.3at High Power Pd And Synchronous Forward Controller With Aux Support
Manufacturer
Linear Technology Corporation
Datasheet

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LTC4269-2
APPLICATIONS INFORMATION
Stray capacitance and potential noise pickup on the R
pin should be minimized by placing the R
close as possible to the R
the R
the R
ground) GND pin. R
Programming Leading Edge Blank Time
For PWM controllers driving external MOSFETs, noise
can be generated at the source of the MOSFET during
gate rise time and some time thereafter. This noise can
potentially exceed the OC and I
LTC4269-2 to cause premature turn-off of SOUT and OUT
pins in addition to false trigger of soft-start. The LTC4269-2
provides a programmable leading edge blanking of the
OC and I
sensing during MOSFET switching.
Blanking is provided in two phases (Figure 12): The fi rst
phase automatically blanks during gate rise time. Gate rise
times can vary depending on MOSFET type. For this reason
the LTC4269-2 performs true ‘leading edge blanking’ by
automatically blanking OC and I
until OUT rises to within 0.5V of V
level of 13V. The second phase of blanking starts after
the leading edge of OUT has been completed. This phase
is programmable by the user with a resistor connected
from the BLANK pin to GND. Typical durations for this
portion of the blanking period are from 45ns at R
24
R
OSC
OSC
OSC
= 9.125k [(4100k/f
Figure 11. Oscillator Frequency, f
SENSE
resistor should be returned directly to the (analog
node as small as possible. The ground side of
500
450
400
350
300
250
200
150
100
50
comparator outputs to avoid false current
100
OSC
150
can be calculated by:
200
R
OSC
OSC
OSC
(kΩ)
250
pin and keeping the area of
SENSE
) – 1]
SENSE
300
IN
pin thresholds of the
or reaches its clamp
comparator outputs
OSC
350
42692 F11
, vs R
OSC
400
OSC
resistor as
BLANK
OSC
OUT
BLANKING
= 10k to 540ns at R
be approximated as:
(see graph in Typical Performance Characteristics)
Programming Current Limit (OC Pin)
The LTC4269-2 uses a precise 107mV sense threshold
at the OC pin to detect overcurrent conditions in the
converter and set a soft-start latch. It is independent of
duty cycle because it is not affected by slope compensa-
tion programmed at the I
the peak current in the primary MOSFET by sensing the
voltage across a sense resistor (R
MOSFET. The overcurrent limit for the converter can be
programmed by:
where:
R
I
N
N
Programming Slope Compensation
The LTC4269-2 uses a current mode architecture to provide
fast response to load transients and to ease frequency
RIPPLE
S
S
P
Blanking (extended) = [45(R
Overcurrent limit = (107mV/R
= sense resistor in source of primary MOSFET
= number of transformer secondary turns
= number of transformer primary turns
=
(AUTOMATIC)
BLANKING
LEADING
P-P
0
EDGE
Figure 12. Leading Edge Blank Timing
ripple current in the output inductor L1
Xns X + 45ns
R
= 10k
(MIN)
BLANK
BLANK
10k < R
(PROGRAMMABLE)
SENSE
= 120k. Blanking duration can
EXTENDED
BLANKING
BLANK
BLANK
pin. The OC pin monitors
S
)(N
S
240k
) in the source of the
P
[X + 45(R
/10k)]ns
/N
S
) – (1/2)(I
CURRENT
BLANK
SENSE
DELAY
100ns
/10k)]ns
RIPPLE
42692 F12
42692f
)

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