ltc4269cdkd-2 Linear Technology Corporation, ltc4269cdkd-2 Datasheet - Page 26

• Manufacturer Part Number: ltc4269cdkd-2
• Description: Ieee 802.3at High Power Pd And Synchronous Forward Controller With Aux Support
• Manufacturer: Linear Technology Corporation

LTC4269-2
APPLICATIONS INFORMATION
To program the volt-second clamp, the following steps
should be taken:
(1) The maximum operational duty cycle of the converter
(2) An initial value for the maximum duty cycle clamp
Note: Since maximum operational duty cycle occurs at
minimum system input voltage (UVLO), the voltage at the
SD_V
where:
(3) The maximum duty cycle clamp calculated in (2)
Example calculation for (2):
Note 1: To achieve the same maximum duty cycle clamp at
100kHz as calculated for 200kHz, the SS_MAXDC voltage
should be reprogrammed by,
26
Max Duty Cycle Clamp (OUT Pin) =
k • 0.522(SS_MAXDC(DC)/SD_V
SS_MAXDC(DC) = V
SD_V
t
k = 1.11 – 5.5e–7 • (f
For R
R
this gives SS_MAXDC(DC) = 1.84V, t
and k = 1
Maximum Duty Cycle Clamp
= 1 • 0.522(1.84/1.32) – (40ns • 200kHz)
= 0.728 – 0.008 = 0.72 (Duty Cycle Clamp = 72%)
SS_MAXDC(DC) (100kHz)
= SS_MAXDC(DC) (200kHz) • k (200kHz)/k (100kHz)
= 1.84 • 1.0/1.055 = 1.74V (k = 1.055 for 100kHz)
DELAY
should be calculated for the given application.
should be calculated using the equation below with a
fi rst pass guess for SS_MAXDC.
should be programmed to be 10% greater than the
maximum operational duty cycle calculated in (1).
Simple adjustment of maximum duty cycle can be
achieved by adjusting SS_MAXDC.
DELAY
SEC
T
SEC
= programmed delay between SOUT and OUT
pin = 1.32V.
= 35.7k, R
= 40k, f
= 1.32V at minimum system input voltage
OSC
B
= 100k, V
= 200kHz and SD_V
REF
OSC
(R
)
B
/(R
REF
T
+ R
= 2.5V,
SEC
B
) – (t
)
DELAY
SEC
DELAY
= 40ns
= 1.32V,
• f
OSC
)
Note 2 : To achieve the same maximum duty cycle clamp
while synchronizing to an external clock at the SYNC pin,
the SS_MAXDC voltage should be reprogrammed as,
Programming Soft-Start Timing
The LTC4269-2 has built-in soft-start capability to provide
low stress controlled start-up from a list of fault condi-
tions that can occur in the application (see Figures 16
and 17). The LTC4269-2 provides true PWM soft-start by
using the SS_MAXDC pin to control soft-start timing. The
proportional relationship between SS_MAXDC voltage and
switch maximum duty cycle clamp allows the SS_MAXDC
pin to slowly ramp output voltage by ramping the maximum
switch duty cycle clamp—until switch duty cycle clamp
seamlessly meets the natural duty cycle of the converter.
A capacitor C
divider from V
cycle clamp, determine soft-start timing (Figure 18).
A soft-start event is triggered for the following faults:
(1) V
(2) SD_V
(3) OC > 107mV (overcurrent condition)
When a soft-start event is triggered, switching at SOUT
and OUT is stopped immediately. A soft-start latch is set
and SS_MAXDC pin is discharged. The SS_MAXDC pin can
only recharge when the soft-start latch has been reset.
Note: A soft-start event caused by (1) or (2) above, also
causes V
SS_MAXDC (DC) (fsync)
= SS_MAXDC (DC) (200kHz) • [(fosc/fsync) +
0.09(fosc/200kHz)0.6]
For SS_MAXDC (DC) (200kHz) = 1.84V for 72%
duty cycle
SS_MAXDC (DC) (fsync = 250kHz) for 72%
duty cycle
= 1.84 • [(200kHz/250kHz) + 0.09(1)0.6]
= 1.638V
IN
< 8.75V, or
REF
SEC
to be disabled and to fall to GND.
< 1.32V (UVLO), or
SS
REF
on the SS_MAXDC pin and the resistor
used to program maximum switch duty
42692f