s29ns01gr Meet Spansion Inc., s29ns01gr Datasheet
s29ns01gr
Related parts for s29ns01gr
s29ns01gr Summary of contents
Page 1
... S29NS-R MirrorBit S29NS01GR, S29NS512R, S29NS256R, S29NS128R 1024/512/256/128 Mb (64/32/16 bit) 1.8 V Burst Simultaneous Read/Write, Multiplexed MirrorBit Flash Memory Data Sheet (Advance Information) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production ...
Page 2
Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all ...
Page 3
... S29NS-R MirrorBit S29NS01GR, S29NS512R, S29NS256R, S29NS128R 1024/512/256/128 Mb (64/32/16 bit) 1.8 V Burst Simultaneous Read/Write, Multiplexed MirrorBit Flash Memory ® Data Sheet (Advance Information) Features Single 1.8 V read/program/erase (1.70–1. MirrorBit Technology Multiplexed Data and Address for reduced I/O count Simultaneous Read/Write operation 32-word Write Buffer ...
Page 4
Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Figures Figure 3.1 Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
... Tables Table 2.1 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Table 6.1 System Versus Flash View of Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 6.2 S29NS01GR Sector and Memory Address Map (No Small Sectors .17 Table 6.3 S29NS512R Sector and Memory Address Map (Uniform: No small sectors .18 Table 6.4 S29NS256R Sector and Memory Address Map (Top Boot .19 Table 6.5 S29NS128R Sector and Memory Address Map (Top Boot .20 Table 6 ...
Page 7
Ordering Information The ordering part number is formed by a valid combination of the following: S29NS 512 R xx 1.1 Valid Combinations Valid Combination list configurations are planned to be ...
Page 8
Input/Output Descriptions & Logic Symbol Table 2.1 identifies the input and output package connections provided on the device. Symbol Amax – A16 A/DQ15 – A/DQ0 I/O F-CE# Input OE# Input WE# Input V Supply CC V Supply CCQ V ...
Page 9
Block Diagrams SSIO VPP RESET# WE# CE# AVD# RDY DQ15–DQ0 ?Amax–A0 Notes: 1. Amax = A25 for NS01GR, A24 for NS512R, A23 for NS256R, A22 ...
Page 10
Physical Dimensions/Connection Diagrams This section shows the I/O designations and package specifications for the S29NS-R. 4.1 Related Documents The following documents contain information relating to the S29NS-R devices. Click on the title www.spansion.com, or request a ...
Page 11
4.2.2 44-Ball Very Thin Fine-Pitch Ball Grid Array, S29NS256R/S29NS128R Figure 4.2 44-Ball Very Thin Fine-Pitch Ball Grid Array, Top View, Balls Facing Down NC NC Note Ball for ...
Page 12
VDH064—64-Ball Very Thin Fine-Pitch Ball Grid Array PACKAGE JEDEC 8. 9.20 mm NOM PACKAGE SYMBOL MIN A 0.84 A1 0.18 A2 0.64 D 8.00 BSC. E 9.20 BSC. D1 4.50 BSC. E1 2.50 BSC ...
Page 13
4.2.4 VDJ044-44-Ball Very Thin Fine-Pitch Ball Grid Array, 6.2mm x 7.7 mm PACKAGE VDJ 044 JEDEC 7. 6.20 mm NOM PACKAGE SYMBOL MIN A 0.86 A1 0.18 A2 0.64 ...
Page 14
Product Overview The S29NS-R family consists of 128 Mbit to 1 Gbit, 1.8-V only, simultaneous read/write, burst-mode, Flash devices. These devices have a 16 bit (word) wide data bus. All read accesses provide 16 bits of data on each ...
Page 15
Address Space Maps There are five address spaces within each device: A Non-Volatile Flash Memory Array used for storage of data that may be randomly accessed by asynchronous or burst ...
Page 16
When writing a command, the address bits between SA and the command specified least significant bits must be Zero to allow for future extension ...
Page 17
... System Address Signals System Byte Address Hex Binary Pattern Flash Word Address Hex Flash Address Signals Table 6.2 S29NS01GR Sector and Memory Address Map (No Small Sectors Bank Size Sector Sector Size (Mbit) ...
Page 18
Table 6.3 S29NS512R Sector and Memory Address Map (Uniform: No small sectors) Bank Size Sector Sector Size (Mbit) Count 32 512 Note All tables have been condensed to show sector-related information for an entire device on a single page. Sectors ...
Page 19
Table 6.4 S29NS256R Sector and Memory Address Map (Top Boot) Bank Size Sector Sector Size (Mbit) Count (KByte) 240 Note: All tables have been condensed to show sector-related ...
Page 20
Table 6.5 S29NS128R Sector and Memory Address Map (Top Boot) Bank Size Sector Sector Size (Mbit) Count (KByte) 120 Note All tables have been condensed to show sector-related information for an entire device on a single page. ...
Page 21
6.3 Device ID and CFI (ID-CFI) There are two traditional methods for systems to identify the type of Flash memory installed in the system. One has been traditionally been called Autoselect ...
Page 22
Common Flash Memory Interface The Common Flash Interface (CFI) specification defines a standardized data structure that may be read from a flash memory device, which allows vendor-specified software algorithms to be used for entire families of devices. The data ...
Page 23
Device Operations This section describes the read and write bus operations, program, erase, simultaneous read/write, handshaking, and reset features of the Flash devices. The address space of the Flash Memory ...
Page 24
Device Operation Table The Device Bus Operations table describes the required state of each control pin for any particular bus operation. The Control Unit (CU) is set to the idle state for reading array data upon device power-up, or ...
Page 25
7.3 Synchronous (Burst) Read Mode and Configuration Register The device is capable of continuous sequential burst operation and linear burst operation of a preset length. In order to use Synchronous (Burst) ...
Page 26
Word Initial Wait wait states Word Initial Wait wait states Word Initial Wait wait states 4 5 ...
Page 27
Word Initial Wait wait states Word Initial Wait wait states May 9, 2008 ...
Page 28
Continuous Burst The device continues to output sequential burst data from the memory array, wrapping around to address 0000000h after it reaches the highest addressable memory location, until the system drives CE# high, RESET# low, or AVD# low in ...
Page 29
Yes Note 1. Required only if device is performing a Continuous Burst operation. 7.3.3 Configuration Register Configuration register (CR) sets various operational parameters associated with burst mode. Upon power-up or hardware ...
Page 30
CR BIt CR.15 CR.14 CR.13 CR.12 CR.11 CR.10 CR.9 CR.8 CR.7 Output Drive Strength CR.6 CR.5 CR.4 CR.3 CR.2 CR.1 CR.0 7.3.3.1 Device Read Mode Configuration Register bit 15 (CR.15) controls whether read accesses via the bus interface are in ...
Page 31
7.3.3.4 RDY Timing Configuration Register bit 8 (CR.8) controls whether the RDY signal indicates valid data on the same cycle that data is valid or one cycle before data is valid. ...
Page 32
Bit 7 Bit 6 Device Ready Erase Suspend Bit. Status Bit Overall status DRB ESSB 1 0 Bits 6:1 only No Erase in valid when Bit Suspension Bit 6:1 only Erase in valid when Bit ...
Page 33
Bit 7 Bit 6 Device Ready Erase Suspend Bit. Status Bit Overall status DRB ESSB 1 Bits 6:1 only X valid when Bit Notes 1. This Register is ...
Page 34
Bit 7 Bit 6 Device Ready Erase Suspend Bit. Status Bit Overall status DRB ESSB 0 Bits 6:1 only X valid when Bit Bits 6:1 only X valid when Bit Bit 6:1 ...
Page 35
7.7 Writing Commands/Command Sequences The device accepts Asynchronous write bus operations. During an asynchronous write bus operation, the system must drive CE# and WE address, AVD# must be ...
Page 36
Write Buffer Programming Write Buffer Programming allows the system to write bytes in one programming operation. The Write Buffer Programming command sequence is initiated by first writing the Write Buffer Load command written at the Sector ...
Page 37
Software Functions and Sample Code Cycle Description 1 Write Buffer Load Command 2 Write Word Count Load Buffer Word N Last Write Buffer to Flash Notes: 1. Base ...
Page 38
Program Suspend/Program Resume Commands The Program Suspend command allows the system to interrupt an embedded programming operation or a Write to Buffer programming operation so that data can read from any non-suspended sector. When the Program Suspend command is ...
Page 39
7.8.3 Sector Erase The sector erase function erases one sector in the memory array. (See does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs ...
Page 40
Software Functions and Sample Code Cycle Description 1 Setup Command 2 Chip Erase Command The following source code example of using the chip erase function. Refer to the Spansion Low Level Driver User’s Guide (available on www.spansion.com) ...
Page 41
Software Functions and Sample Code Cycle 1 The following source code example of using the erase suspend function. Refer to the Spansion Low Level Driver User’s Guide (available ...
Page 42
Handshaking The handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the RDY (Ready) pin, which is a dedicated output controlled by CE#. The NS01GR has an option for two ...
Page 43
Sector Protection/Unprotection The Sector Protection/Unprotection feature disables or enables programming or erase operations in one or multiple sectors and can be implemented through software and/or hardware methods, which are independent ...
Page 44
Hardware Data Protection Methods There are additional hardware methods by which intended or accidental erasure of any sectors can be prevented via hardware means. The following subsections describes these methods: 8.3.1 V Method PP Once V input is set ...
Page 45
8.5.2 Customer Secure Silicon Region The Customer Secure Silicon Region is typically shipped unprotected, Customer SSR Lock Bit (bit 0) set to a one, allowing customers to utilize that sector in ...
Page 46
Cycle Exit Cycle /* Example: SecSi Sector Exit Command */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0; 9. Power Conservation Modes 9.1 Standby Mode In the standby mode current consumption is greatly reduced, and the outputs (A/DQ15-A/DQ0) are placed ...
Page 47
10. Electrical Specifications 10.1 Absolute Maximum Ratings Storage Temperature Plastic Packages Ambient Temperature with Power Applied Voltage with Respect to Ground: All Inputs and I/Os except as noted below (Note 1) ...
Page 48
DC Characteristics 10.3.1 CMOS Compatible Parameter Description I Input Load Current LI I Output Leakage Current Active burst Read Current CCB Non-active Output IO1 Standby IO2 IO V Active Asynchronous ...
Page 49
10.4 AC Test Conditions Input level Input comparison level Output data comparison level Load capacitance ( Transition time (t ) (input rise and fall times) T Transition time (t ...
Page 50
Key to Switching Waveforms Waveform 10.6 V Power Up CC Parameter t VCS t VIOS t Time between RESET# (high) and CE# (low) RH Notes 1. RESET# must be high after V ≥ – 200 mV ...
Page 51
10.7 CLK Characterization Parameter f CLK t CLK Notes 1. DC for operations other than synchronous burst read. See AC Characteristics Table. 2. Clock jitter of +-5% ...
Page 52
CE# 1 CLK t AVDS AVD# t ACS Amax– AC A16 t ACH A/DQ15– AC A/DQ0 OE Hi-Z RDY 10.8.2 AC Characteristics–Asynchronous Read Access Time from CE# Low Asynchronous Access Time from address valid Read Cycle Time AVD# ...
Page 53
CE# OE# WE# A/DQ15 – A/DQ0 Amax A16 – AVD# Hi-Z RDY Notes 1. AVD# Transition occurs after CE# is driven to Low and Valid Address Transition occurs before AVD# is ...
Page 54
AC Characteristics–Erase/Program Timing Parameter WE# Cycle Time (1) AVD# low pulse width Address Setup to rising edge of AVD# Address Hold from rising edge of AVD# Read Recovery Time Before Write Data Setup to rising edge of WE# Data ...
Page 55
10.8.4 Hardware Reset (Reset#) Parameter JEDEC CE#, OE# RESET# Address 7C (hex) CLK (stays high) AVD# RDY (Note 1) RDY (Note 2) Data OE#, (stays low) CE# Notes 1. RDY active ...
Page 56
Figure 10.12 Latency with Boundary Crossing into Bank Performing Embedded Operation Address 7C (hex) CLK (stays high) AVD# RDY (Note 1) RDY (Note 2) Data OE#, (stays low) CE# Notes 1. RDY active with data (CR the ...
Page 57
10.8.5 Wait State Configuration Register Setup Data AVD# OE# CLK 0 Configuration Register 0000 = 0001 = 0010 = 0011 = CR.14 0100 = CR.13 0101 = CR.12 CR.11 0110 = ...
Page 58
Command Sequence CE# OE# WE# t WPH Data Addresses t AVD# Note Breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while checking the status of the program or erase operation in the busy ...
Page 59
10.8.6 Erase and Programming Performance Parameter Sector Erase Time (Note 7) Chip Erase Time (Note 7) Single Word Program Time (using Program Buffer) Effective Word Programming Time using Program Write Buffer ...
Page 60
Appendix This section contains information relating to software control or interfacing with the Flash device. 11.1 Command Definitions All values are in hexadecimal. The S29NS-R family of devices are 16-bit word address oriented. Most system address buses, regardless of ...
Page 61
Command Sequence Addr (SA) 555 SSR Lock Entry 1 (7) (10) (SA) AAA (SA) 555 Write Buffer Load (8) 3 (SA) AAA (SA) 555 Buffer to Flash 1 (SA) AAA SSR ...
Page 62
Device ID and Common Flash Memory Interface Address Map The Device ID fields occupy the first 32 bytes of address space followed by the Common Flash Interface data structure. The Common Flash Interface (CFI) specification defines a standardized data ...
Page 63
Word Offset Byte Offset Address Address (SA) + 10h (SA) + 20h (SA) + 11h (SA) + 22h (SA) + 12h (SA) + 24h (SA) + 13h (SA) + 26h (SA) ...
Page 64
Word Offset Byte Offset Address Address (SA) + 27h (SA) + 4Eh (SA) + 28h (SA) + 50h (SA) + 29h (SA) + 52h (SA) + 2Ah (SA) + 54h (SA) + 2Bh (SA) + 56h (SA) + 2Ch (SA) ...
Page 65
Word Offset Byte Offset Address Address (SA) + 40h (SA) + 80h (SA) + 41h (SA) + 82h (SA) + 42h (SA) + 84h (SA) + 43h (SA) + 86h (SA) ...
Page 66
Word Offset Byte Offset Address Address (SA) + 51h (SA) + A2h (SA) + 52h (SA) + A4h (SA) + 53h (SA) + A6h (SA) + 54h (SA) + A8h (SA) + 55h (SA) + AAh (SA) + 56h (SA) ...
Page 67
12. Revision History Section Revision 01 (December 12, 2007) Initial release Revision 02 (February 27, 2008) DC Characteristics Modified V AC Characteristics Updated Section 10.9.1 for timing parameters (t Revision 03 ...
Page 68
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated ...