s908qc16g0cdte Freescale Semiconductor, Inc, s908qc16g0cdte Datasheet
s908qc16g0cdte
Related parts for s908qc16g0cdte
s908qc16g0cdte Summary of contents
Page 1
MC68HC08QY4 MC68HC08QT4 MC68HC08QY2 MC68HC08QT2 MC68HC08QY1 MC68HC08QT1 Data Sheet M68HC08 Microcontrollers MC68HC08QY4 Rev. 2 3/2010 freescale.com ...
Page 2
...
Page 3
... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2006–2010. All rights reserved. Freescale Semiconductor MC68HC08QY/QT Family Data Sheet, Rev ...
Page 4
Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Revision Date Level October, N/A Initial release 2005 1.7 Unused Pin ...
Page 5
List of Chapters Chapter 1 General Description ...
Page 6
List of Chapters 6 MC68HC08QY/QT Family Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 7
Table of Contents 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 8
Table of Contents 3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 9
Power-On Reset ...
Page 10
Table of Contents 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 11
Bus Clock Times 4 (BUSCLKX4 ...
Page 12
Table of Contents 13.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 13
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 14
Table of Contents 16.11 1.8-V to 3.6-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 15
Chapter 1 General Description 1.1 Introduction The MC68HC08QY4 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a ...
Page 16
General Description • 6-channel, 10-bit analog-to-digital converter (ADC) with internal bandgap reference channel (ADC10) • bidirectional input/output (I/O) lines and one input only: – Six shared with KBI – Six shared with ADC – Two shared with ...
Page 17
PTA0/TCH0/AD0//KBI0 PTA1/TCH1/AD1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 MC68HC08QY4 128 BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device PTA[0:5]: Higher current ...
Page 18
General Description PTA5/OSC1/KBI5 2 7 PTA4/OSC2/KBI4 3 6 PTA3/RST/KBI3 5 4 8-PIN ASSIGNMENT MC68HC08QT1 SOIC PTB7 2 15 PTB6 3 14 PTA5/OSC1/KBI5 4 13 PTA4/OSC2/KBI4 5 12 PTB5 6 11 PTB4 7 ...
Page 19
Pin Name V Power supply DD V Power supply ground SS PTA0 — General purpose I/O port AD0 — A/D channel 0 input PTA0 TCH0 — Timer Channel 0 I/O KBI0 — Keyboard interrupt input 0 PTA1 — General purpose ...
Page 20
General Description 1.6 Pin Function Priority Table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin. Upon reset all pins come up as input ports regardless of the priority table. Table 1-3. Function ...
Page 21
Chapter 2 Memory 2.1 Introduction The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map is shown in Figure 2-1. 2.2 Unimplemented Memory Locations Executing code from an unimplemented location will cause an illegal address ...
Page 22
Memory $0000 DIRECT PAGE REGISTERS ↓ 64 BYTES $003F $0040 RESERVED ↓ 64 BYTES $007F $0080 RAM ↓ 128 BYTES $00FF $0100 UNIMPLEMENTED ↓ 60,160 BYTES $EBFF $EC00 AUXILIARY ROM ↓ 512 BYTES $EDFF $EE00 ROM ↓ 4096 BYTES $FDFF ...
Page 23
Addr. Register Name Read: Port A Data Register $0000 (PTA) Write: See page 98. Reset: Read: Port B Data Register $0001 (PTB) Write: See page 100. Reset: $0002 ↓ Reserved $0003 Read: Data Direction Register A $0004 (DDRA) Write: See ...
Page 24
Memory Addr. Register Name Read: IRQ Status and Control $001D Register (INTSCR) Write: See page 75. Reset: Read: Configuration Register 2 (1) $001E (CONFIG2) Write: See page 51. Reset: Read: Configuration Register 1 (1) $001F (CONFIG1) Write: See page 52. ...
Page 25
Addr. Register Name Read: TIM Channel 1 Status and $0028 Control Register (TSC1) Write: See page 129. Reset: Read: TIM Channel 1 $0029 Register High (TCH1H) Write: See page 131. Reset: Read: TIM Channel 1 $002A Register Low (TCH1L) Write: ...
Page 26
Memory Addr. Register Name Read: Break Status Register $FE00 (BSR) Write: See page 136. Reset: Read: SIM Reset Status Register $FE01 (SRSR) Write: See page 116. POR: Read: Break Auxiliary $FE02 Register (BRKAR) Write: See page 137. Reset: Read: Break ...
Page 27
Addr. Register Name Read: LVI Status Register $FE0C (LVISR) Write: See page 85. Reset: $FE0D ↓ Reserved $FE0F $FEBE ↓ Reserved $FEBF Read: Internal Oscillator Trim $FFC0 Write: (Factory Programmed) Reset: $FFC1 Reserved Read: COP Control Register $FFFF (COPCTL) Write: ...
Page 28
Memory Vector Priority Vector Address Lowest IF22– $FFD0,1– IF16 $FFDC,D IF15 $FFDE,F IF14 $FFE0,1 IF13 IF12 IF11 IF10 IF9 IF8 $FFEC,D IF7 IF6 IF5 $FFF2,3 IF4 $FFF4,5 IF3 $FFF6,7 IF2 IF1 $FFFA,B — $FFFC,D — $FFFE,F Highest 2.6 Random-Access Memory ...
Page 29
Read-Only Memory (ROM) The ROM memory is intended primarily for program storage. Consult Table 1-1. Summary of Device Variations Figure 2-1 for user program ROM locations. Forty-eight bytes of user vectors, $FFD0–$FFFF, are dedicated to user-defined reset and interrupt ...
Page 30
Memory 30 MC68HC08QY/QT Family Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 31
Chapter 3 10-Bit Analog-to-Digital Converter (ADC10) Module 3.1 Introduction This section describes the 10-bit successive approximation analog-to-digital converter (ADC10). The ADC10 module shares its pins with general-purpose input/output (I/O) port pins. See port location of these shared pins. The ADC10 ...
Page 32
Analog-to-Digital Converter (ADC10) Module PTA0/TCH0/AD0//KBI0 PTA1/TCH1/AD1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 MC68HC08QY4 128 BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up device All port pins have programmable pull ...
Page 33
ADCSC 1 2 MCU STOP ADHWT AD0 ADVIN ADn V REFH V REFL The ADC10 can perform an analog-to-digital conversion on one of the software selectable channels. The output of the input multiplexer (ADVIN) is converted by a successive approximation ...
Page 34
Analog-to-Digital Converter (ADC10) Module clocks are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the ADIV[1:0] bits and can be divide- 3.3.2 Input Select and ...
Page 35
Upon reset or when a conversion is otherwise aborted, the ADC10 module will enter a low power, inactive state. In this state, all internal clocks and references are disabled. This state is entered asynchronously and immediately upon aborting of a ...
Page 36
Analog-to-Digital Converter (ADC10) Module 3.3.4 Sources of Error Several sources of error exist for ADC conversions. These are discussed in the following sections. 3.3.4.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the ...
Page 37
Code Width and Quantization Error The ADC10 quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step ideally has the same height (1 code) and width. The width is defined as the delta between the ...
Page 38
Analog-to-Digital Converter (ADC10) Module 3.4 Interrupts When AIEN is set, the ADC10 is capable of generating a CPU interrupt after each conversion. A CPU interrupt is generated when the conversion completes (indicated by COCO being set). COCO will set ...
Page 39
To protect status bits during the break state, write BCFE. With BCFE cleared (its default state), software can read and write registers during the break state without affecting status bits. Some status bits have a two-step read/write ...
Page 40
Analog-to-Digital Converter (ADC10) Module 3.7.4 ADC10 Voltage Reference Low Pin ( the power supply for setting the low-reference voltage for the converter. In some packages, REFL V is connected internally to V REFL potential ...
Page 41
ACLKEN is clear), ADCLK is written, or until ADCSC is written again. If stop is entered (with ACLKEN low), continuous conversions will cease and can be restarted only with a write to ADCSC. Any write to ADCSC ...
Page 42
Analog-to-Digital Converter (ADC10) Module 3.8.2 ADC10 Result High Register (ADRH) This register holds the MSBs of the result and is updated each time a conversion completes. All other bits read as 0s. Reading ADRH prevents the ADC10 from transferring ...
Page 43
ADC10 Clock Register (ADCLK) This register selects the clock frequency for the ADC10 and the modes of operation. Bit 7 Read: ADLPC ADIV1 Write: Reset: 0 Figure 3-7. ADC10 Clock Register (ADCLK) ADLPC — ADC10 Low-Power Configuration Bit ADLPC ...
Page 44
Analog-to-Digital Converter (ADC10) Module ADLSMP — Long Sample Time Configuration This bit configures the sample time of the ADC10 to either 3.5 or 23.5 ADCK clock cycles. This adjusts the sample period to allow higher impedance inputs to be ...
Page 45
Chapter 4 Auto Wakeup Module (AWU) 4.1 Introduction This section describes the auto wakeup module (AWU). The AWU generates a periodic interrupt during stop mode to wake the part up without requiring an external signal. AWU. COPRS (FROM CONFIG1) OSCENINSTOP ...
Page 46
Auto Wakeup Module (AWU) 4.3 Functional Description The function of the auto wakeup logic is to generate periodic wakeup requests to bring the microcontroller unit (MCU) out of stop mode. The wakeup requests are treated as regular keyboard interrupt requests, ...
Page 47
Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 4.5.1 Wait Mode The AWU module is inactive in wait mode. 4.5.2 Stop Mode When the AWU module is enabled (AWUIE = 1 in ...
Page 48
Auto Wakeup Module (AWU) 4.6.2 Keyboard Status and Control Register The keyboard status and control register (KBSCR): • Flags keyboard/auto wakeup interrupt requests • Acknowledges keyboard/auto wakeup interrupt requests • Masks keyboard/auto wakeup interrupt requests Bit 7 Read: 0 Write: ...
Page 49
AWUIE — Auto Wakeup Interrupt Enable Bit This read/write bit enables the auto wakeup interrupt input to latch interrupt requests. Reset clears AWUIE Auto wakeup enabled as interrupt input 0 = Auto wakeup not enabled as interrupt input ...
Page 50
Auto Wakeup Module (AWU) COPRS (In Stop Mode) — Auto Wakeup Period Selection Bit, depends on OSCSTOPEN in CONFIG2 and bus clock source (BUSCLKX2 Auto wakeup short cycle = 512 × (INTRCOSC or BUSCLKX2 Auto wakeup ...
Page 51
Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers enable or disable the following options: Stop mode recovery time (32 × BUSCLKX4 cycles or 4096 × BUSCLKX4 cycles) • • ...
Page 52
Configuration Register (CONFIG) IRQPUD — IRQ Pin Pullup Control Bit 1 = Internal pullup is disconnected 0 = Internal pullup is connected between IRQ pin and V IRQEN — IRQ Pin Function Selection Bit 1 = Interrupt request function active ...
Page 53
LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module LVI module power disabled 0 = LVI module power enabled LVITRIP — LVI Trip Point Selection Bit LVITRIP selects the voltage operating mode of the LVI module. ...
Page 54
Configuration Register (CONFIG) 54 MC68HC08QY/QT Family Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 55
Chapter 6 Computer Operating Properly (COP) 6.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by ...
Page 56
Computer Operating Properly (COP) The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 BUSCLKX4 ...
Page 57
COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1 (CONFIG1). See Chapter 5 Configuration Register 6.4 Interrupts The COP does not generate CPU interrupt requests. 6.5 ...
Page 58
Computer Operating Properly (COP) 58 MC68HC08QY/QT Family Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 59
Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction ...
Page 60
Central Processor Unit (CPU 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 Read: Write: Reset: 7.3.2 Index Register The ...
Page 61
Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least ...
Page 62
Central Processor Unit (CPU) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following ...
Page 63
Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00 Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the ...
Page 64
Central Processor Unit (CPU) 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instruction set. Table 7-1. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr ADC opr,X Add with ...
Page 65
Table 7-1. Instruction Set Summary (Sheet Source Operation Form Branch if Higher or Same BHS rel (Same as BCC) BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low BIT #opr BIT opr ...
Page 66
Central Processor Unit (CPU) Table 7-1. Instruction Set Summary (Sheet Source Operation Form CLR opr CLRA CLRX CLRH Clear CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X Compare A with M ...
Page 67
Table 7-1. Instruction Set Summary (Sheet Source Operation Form JMP opr JMP opr JMP opr,X Jump JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X LDA #opr LDA opr ...
Page 68
Central Processor Unit (CPU) Table 7-1. Instruction Set Summary (Sheet Source Operation Form PULA Pull A from Stack PULH Pull H from Stack PULX Pull X from Stack ROL opr ROLA ROLX Rotate Left through Carry ROL ...
Page 69
Table 7-1. Instruction Set Summary (Sheet Source Operation Form SWI Software Interrupt TAP Transfer A to CCR TAX Transfer TPA Transfer CCR to A TST opr TSTA TSTX Test for Negative or Zero TST ...
Page 70
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
Page 71
Chapter 8 External Interrupt (IRQ) 8.1 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. IRQ functionality is enabled by setting configuration register 2 (CONFIG2) IRQEN bit accordingly. A zero disables the IRQ function and IRQ will assume ...
Page 72
External Interrupt (IRQ) PTA0/TCH0/AD0//KBI0 PTA1/TCH1/AD1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 MC68HC08QY4 128 BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device ...
Page 73
RESET ACK IRQ VECTOR FETCH DECODER V DD INTERNAL PULLUP DEVICE IRQ 8.3.1 MODE = 1 If the MODE bit is set, the IRQ pin is both falling edge sensitive and low level sensitive. With MODE set, both of the ...
Page 74
External Interrupt (IRQ) 8.4 Interrupts The following IRQ source can generate interrupt requests: • Interrupt flag (IRQF) — The IRQF bit is set when the IRQ pin is asserted based on the IRQ mode. The IRQ interrupt mask bit, IMASK, ...
Page 75
Registers The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: • Shows the state of the IRQ flag • Clears the IRQ latch • Masks the IRQ interrupt request • Controls ...
Page 76
External Interrupt (IRQ) 76 MC68HC08QY/QT Family Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 77
Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction The keyboard interrupt module (KBI) provides independently maskable external interrupts. The KBI shares its pins with general-purpose input/output (I/O) port pins. See of these shared pins. 9.2 Features Features of the keyboard ...
Page 78
Keyboard Interrupt Module (KBI) PTA0/TCH0/AD0//KBI0 PTA1/TCH1/AD1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 MC68HC08QY4 128 BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up device All port pins have programmable pull up ...
Page 79
INTERNAL BUS VECTOR FETCH DECODER ACKK RESET 1 0 KBI0 S KBIE0 TO PULLUP/ PULLDOWN ENABLE KBIP0 1 0 KBIx S KBIEx TO PULLUP/ KBIPx PULLDOWN ENABLE AWUIREQ (SEE Figure 4-1) Figure 9-2. Keyboard Interrupt Block Diagram The KBI vector ...
Page 80
Keyboard Interrupt Module (KBI) 9.3.2 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pullup or pulldown device to pull the pin to its deasserted level. Therefore a false interrupt can occur as soon ...
Page 81
I/O Signals The KBI module can share its pins with the general-purpose I/O pins. See are shared. 9.7.1 KBI Input Pins (KBIx:KBI0) Each KBI pin is independently programmable as an external interrupt source. KBI pin polarity can be controlled ...
Page 82
Keyboard Interrupt Module (KBI) 9.8.2 Keyboard Interrupt Enable Register (KBIER) KBIER enables or disables each keyboard interrupt pin. Bit 7 Read: 0 AWUIE Write: Reset Unimplemented Figure 9-4. Keyboard Interrupt Enable Register (KBIER) KBIE5–KBIE0 — Keyboard Interrupt Enable ...
Page 83
Chapter 10 Low-Voltage Inhibit (LVI) 10.1 Introduction The low-voltage inhibit (LVI) module is provided as a system protection mechanism to prevent the MCU from operating below a certain operating supply voltage level. The module has several configuration options to allow ...
Page 84
Low-Voltage Inhibit (LVI) The LVI module contains a bandgap reference circuit and comparator. When the LVITRIP bit is cleared, the default state at power-on reset, V trip points are specified in 16.5 5-V DC Electrical and 16.11 1.8-V to 3.6-V ...
Page 85
LVI Interrupts The LVI module does not generate interrupt requests. 10.5 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. 10.5.1 Wait Mode If enabled, the LVI module remains active in wait mode. ...
Page 86
Low-Voltage Inhibit (LVI) 86 MC68HC08QY/QT Family Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 87
Chapter 11 Oscillator Module (OSC) 11.1 Introduction The oscillator (OSC) module is used to provide a stable clock source for the MCU system and bus. The OSC shares its pins with general-purpose input/output (I/O) port pins. See location of these ...
Page 88
Oscillator Module (OSC) PTA0/TCH0/AD0//KBI0 PTA1/TCH1/AD1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 MC68HC08QY4 128 BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device ...
Page 89
Internal Signal Definitions The following signals and clocks are used in the functional description and figures of the OSC module. 11.3.1.1 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and disables the XTAL ...
Page 90
Oscillator Module (OSC) Figure 11-3 shows how BUSCLKX4 is derived from INTCLK and OSC2 can output BUSCLKX4 by setting OSC2EN. 11.3.2.1 Internal Oscillator Trimming OSCTRIM allows a clock period adjustment of +127 and –128 steps. Increasing the OSCTRIM value increases ...
Page 91
XTAL Oscillator The XTAL oscillator circuit is designed for use with an external crystal or ceramic resonator to provide an accurate clock source. In this configuration, the OSC2 pin is dedicated to the external crystal circuit. The OSC2EN bit ...
Page 92
Oscillator Module (OSC) 11.3.5 RC Oscillator The RC oscillator circuit is designed for use with an external resistor (R a tolerance within 25% of the expected frequency. See The capacitor (C) for the RC oscillator is internal to the MCU. ...
Page 93
OSC During Break Interrupts There are no status flags associated with the OSC module. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break ...
Page 94
Oscillator Module (OSC) 11.8 Registers The oscillator module contains two registers: • Oscillator status and control register (OSCSC) • Oscillator trim register (OSCTRIM) 11.8.1 Oscillator Status and Control Register The oscillator status and control register (OSCSC) contains the bits for ...
Page 95
ECFS1:ECFS0 — External Crystal Frequency Select Bits These read/write bits enable the specific amplifier for the crystal frequency range. Refer to oscillator characteristics table in the Electricals section for information on maximum external clock frequency versus supply voltage. ECFS1 0 ...
Page 96
Oscillator Module (OSC) 96 MC68HC08QY/QT Family Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 97
Chapter 12 Input/Output Ports (PORTS) 12.1 Introduction The MC68HC08QY1, MC68HC08QY2 and MC68HC08QY4 have thirteen bidirectional input-output (I/O) pins and one input only pin. The MC68HC08QT1, MC68HC08QT2 and MC68HC08QT4 has five bidirectional I/O pins and one input only pin. All I/O ...
Page 98
Input/Output Ports (PORTS) 12.3.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the six port A pins. Bit 7 Read: AWUL R Write: Reset: = Unimplemented PTA[5:0] — Port A Data ...
Page 99
READ DDRA WRITE DDRA WRITE PTA READ PTA When DDRAx reading PTA reads the PTAx data latch. When DDRAx reading PTA reads the logic level on the PTAx pin. The data latch can always ...
Page 100
Input/Output Ports (PORTS) 12.3.4 Port A Summary Table The following table summarizes the operation of the port A pins when used as a general-purpose input/output pins. PTAPUE DDRA PTA Bit Bit Bit ( ...
Page 101
Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing DDRB bit enables the output buffer for the corresponding port B pin; a ...
Page 102
Input/Output Ports (PORTS) 12.4.3 Port B Input Pullup Enable Register The port B input pullup enable register (PTBPUE) contains a software configurable pullup device for each of the eight port B pins. Each bit is individually configurable and requires the ...
Page 103
Chapter 13 System Integration Module (SIM) 13.1 Introduction This section describes the system integration module (SIM), which supports external and/or internal interrupts. Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. ...
Page 104
System Integration Module (SIM) STOP/WAIT CONTROL V DD CLOCK CONTROL INTERNAL PULL-UP RESET POR CONTROL PIN LOGIC RESET PIN CONTROL SIM RESET STATUS REGISTER INTERRUPT CONTROL AND PRIORITY DECODE 13.3 SIM Bus Clock Control and Generation The bus clock generator ...
Page 105
Bus Timing In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four. 13.3.2 Clock Start-Up from POR When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive ...
Page 106
System Integration Module (SIM) 13.4.2 Active Resets from Internal Sources The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in the CONFIG2 register enables the pin for the reset function. This section ...
Page 107
Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4 cycles later, the CPU ...
Page 108
System Integration Module (SIM) If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST ...
Page 109
Exception Control Normal sequential program execution can be changed in three different ways: 1. Interrupts a. Maskable hardware CPU interrupts b. Non-maskable software interrupt instruction (SWI) 2. Reset 3. Break interrupts 13.6.1 Interrupts An interrupt temporarily changes the sequence ...
Page 110
System Integration Module (SIM) YES (AS MANY INTERRUPTS AS EXIST ON CHIP) 110 FROM RESET YES BREAK INTERRUPT? I BIT SET BIT SET? NO YES IRQ INTERRUPT? NO YES TIMER INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR FETCH ...
Page 111
MODULE INTERRUPT I BIT ADDRESS BUS DUMMY SP DATA BUS DUMMY R/W MODULE INTERRUPT I BIT ADDRESS BUS SP – 4 DATA BUS R/W INT1 INT2 Figure 13-10 Freescale Semiconductor SP – – – ...
Page 112
System Integration Module (SIM) 13.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. A software interrupt pushes PC onto the ...
Page 113
Interrupt Status Register 1 Bit 7 Read: IF6 Write: R Reset Reserved Figure 13-11. Interrupt Status Register 1 (INT1) IF1 and IF3–IF6 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources ...
Page 114
System Integration Module (SIM) 13.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 13.6.4 Break Interrupts The break module can stop normal program flow at a software programmable break point by asserting its break ...
Page 115
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. ...
Page 116
System Integration Module (SIM) The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery then used to time the recovery period. Figure 13-18 shows the stop mode recovery ...
Page 117
POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST POR or read of SRSR ...
Page 118
System Integration Module (SIM) 118 MC68HC08QY/QT Family Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 119
Chapter 14 Timer Interface Module (TIM) 14.1 Introduction This section describes the timer interface module (TIM). The TIM module is a 2-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. The TIM module shares ...
Page 120
Timer Interface Module (TIM) PTA0/TCH0/AD0//KBI0 PTA1/TCH1/AD1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 MC68HC08QY4 128 BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up device All port pins have programmable pull up ...
Page 121
TCLK TCLK (IF AVAILABLE) INTERNAL PRESCALER BUS CLOCK TSTOP TRST 16-BIT COUNTER TCNTH:TCNTL 16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH 14.3.3.1 Unbuffered Output Compare Any output compare channel can generate ...
Page 122
Timer Interface Module (TIM) the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 14.3.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare ...
Page 123
The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle ...
Page 124
Timer Interface Module (TIM) channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 14.3.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure ...
Page 125
Interrupts The following TIM sources can generate interrupt requests: • TIM overflow flag (TOF) — The TOF bit is set when the counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable ...
Page 126
Timer Interface Module (TIM) 14.7 I/O Signals The TIM module can share its pins with the general-purpose I/O pins. See that are shared. 14.7.1 TIM Channel I/O Pins (TCH1:TCH0) Each channel I/O pin is programmable independently as an input capture ...
Page 127
If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Writing TOF has no ...
Page 128
Timer Interface Module (TIM) 14.8.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into ...
Page 129
TIM Channel Status and Control Registers Each of the TIM channel status and control registers does the following: • Flags input captures and output compares • Enables input capture and output compare interrupts • Selects input capture, output compare, ...
Page 130
Timer Interface Module (TIM) Setting MS0B causes the contents of TSC1 to be ignored by the TIM and reverts TCH1 to general-purpose I/ Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA — Mode ...
Page 131
TOVx — Toggle-On-Overflow Bit When channel output compare channel, this read/write bit controls the behavior of the channel x output when the counter overflows. When channel input capture channel, TOVx has no effect. 1 ...
Page 132
Timer Interface Module (TIM) 132 MC68HC08QY/QT Family Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 133
Chapter 15 Development Support 15.1 Introduction This section describes the break module, the monitor module (MON), and the monitor mode entry methods. 15.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow at ...
Page 134
Development Support PTA0/TCH0/AD0//KBI0 PTA1/TCH1/AD1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 MC68HC08QY4 128 BYTES USER RAM POWER SUPPLY RST, IRQ: Pins have internal pull up device All port pins have programmable pull up device PTA[0:5]: ...
Page 135
The break interrupt timing is: • When a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. • When a break address is placed at ...
Page 136
Development Support 15.2.2 Break Module Registers These registers control and monitor operation of the break module: • Break status and control register (BRKSCR) • Break address register high (BRKH) • Break address register low (BRKL) • Break status register (BSR) ...
Page 137
Break Auxiliary Register The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the MCU state of break interrupt with monitor mode. Bit 7 Read: 0 Write: Reset ...
Page 138
Development Support BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE ...
Page 139
CONDITIONS FROM Table 15-1 DEBUGGING Figure 15-9. Simplified Monitor Mode Entry Flowchart Freescale Semiconductor POR RESET YES IRQ = V ? TST NO NORMAL USER MODE MONITOR MODE HOST SENDS 8 SECURITY BYTES YES IS RESET POR? NO ENABLE ROM ...
Page 140
Development Support MAX232 μ C1– μF 6 V– 5 C2– 1 μF DB9 Figure 15-10. Monitor Mode Circuit (External Clock, ...
Page 141
Table 15-1. Monitor Mode Signal Requirements and Options IRQ RST Reset Mode (PTA2) (PTA3) Vector Normal TST DD Monitor User MON08 V RST TST Function — [4] [6] [Pin No.] ...
Page 142
Development Support Table 15-2 summarizes the differences between user mode and monitor mode regarding vectors. Modes Reset Vector High User $FFFE Monitor $FEFE 15.3.1.3 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit ...
Page 143
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of ...
Page 144
Development Support Table 15-4. WRITE (Write Memory) Command Description Write byte to memory Operand 2-byte address in high-byte:low-byte order; low byte followed by data byte Data Returned None Opcode $49 FROM HOST WRITE WRITE ECHO Table 15-5. IREAD (Indexed Read) ...
Page 145
Table 15-7. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Returns incremented stack pointer value ( high-byte:low-byte Data Returned order Opcode $0C FROM HOST ECHO Table 15-8. RUN (Run User Program) Command Description Executes ...
Page 146
Development Support 15.3.2 Security A security feature discourages unauthorized reading of ROM locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. ...
Page 147
Chapter 16 Electrical Specifications 16.1 Introduction This section contains electrical and timing specifications. 16.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. This device is not ...
Page 148
Electrical Specifications 16.3 Functional Operating Range Characteristic Operating temperature range Operating voltage range 16.4 Thermal Characteristics Characteristic Thermal resistance 8-pin SOIC 16-pin SOIC 16-pin TSSOP I/O pin power dissipation (1) Power dissipation (2) Constant Average junction temperature Maximum junction temperature ...
Page 149
Characteristic Input high voltage PTA0–PTA5, PTB0–PTB7 Input low voltage PTA0–PTA5, PTB0–PTB7 (3) Input hysteresis (3) (4) (5) (6) DC injection current Single pin limit V > < Total MCU limit, includes sum ...
Page 150
Electrical Specifications 16.6 Typical 5-V Output Drive Characteristics 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 Figure 16-1. Typical 5-Volt Output High Voltage 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 Figure 16-2. Typical 5-Volt Output ...
Page 151
Control Timing Characteristic Internal operating frequency Internal clock period (1 (2) RST input pulse width low IRQ interrupt pulse width low (edge-triggered) (2) IRQ interrupt pulse period 4.5 to 5.5 Vdc ...
Page 152
Electrical Specifications (1) Characteristic Input low voltage PTA0–PTA5, PTB0–PTB7 (3) Input hysteresis (3) (4) (5) (6) DC injection current Single pin limit V > < Total MCU limit, includes sum of all stressed ...
Page 153
Typical 3-V Output Drive Characteristics 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 Figure 16-4. Typical 3-Volt Output High Voltage 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 Figure 16-5. Typical 3-Volt Output Low Voltage Freescale Semiconductor -5 -10 ...
Page 154
Electrical Specifications 16.10 3-V Control Timing Characteristic Internal operating frequency Internal clock period (1 (2) RST input pulse width low IRQ interrupt pulse width low (edge-triggered) (2) IRQ interrupt pulse period 2.7 to 3.3 Vdc, ...
Page 155
DC Electrical Characteristics (1) Characteristic Output high voltage I = –0.6 mA, all I/O pins Load I = –2.0 mA, all I/O pins Load I = –5.0 mA, PTA0, PTA1, PTA3–PTA5 only Load Maximum combined I ...
Page 156
Electrical Specifications 16.12 Typical 2-V Output Drive Characteristics 1.2 1 0.8 0.6 0.4 0 Figure 16-7. Typical 2-Volt Output High Voltage 1.2 1 0.8 0.6 0.4 0 Figure 16-8. Typical 2-Volt Output Low Voltage 156 -2 ...
Page 157
Control Timing Characteristic Internal operating frequency Internal clock period (1 (2) RST input pulse width low IRQ interrupt pulse width low (edge-triggered) (2) IRQ interrupt pulse period Vdc ...
Page 158
Electrical Specifications 16.14 Oscillator Characteristics Characteristic (1) Internal oscillator frequency ICFS1:ICFS0 = 00 ICFS1:ICFS0 = 01 ICFS1:ICFS0 = 10 (not allowed if V Trim accuracy - fixed voltage and temperature Deviation from trimmed Internal oscillator = ± 10 ...
Page 159
Characteristic AWU module, internal RC oscillator frequency 1. Bus frequency oscillator frequency divided Value is deviation from 25•C and midpoint of voltage range. Factory trimming is done at @25•C and at voltage as ...
Page 160
Electrical Specifications Figure 16-11. RC versus Frequency (3 Volts @ 25° Figure 16-12. RC versus Frequency (2 Volts @ 25°C) 160 ...
Page 161
Supply Current Characteristics (1) Characteristic (3) Run mode V supply current DD (4) Wait mode V supply current DD (5) Stop mode V supply current DD –40 to 85°C –40 to 125°C 25°C with auto wake-up enabled Incremental current ...
Page 162
Electrical Specifications Figure 16-13. Typical 5-Volt Run Current 2.5 2 1 Figure 16-14. Typical 3-Volt Run Current 162 FREQUENCY versus Bus Frequency (25• ...
Page 163
Figure 16-15. Typical 2-Volt Run Current Freescale Semiconductor BUS FREUQENCY (MHz) versus Bus Frequency (25•C) MC68HC08QY/QT Family Data Sheet, Rev. 2 Supply Current Characteristics Internal OSC (No A/D) Internal ...
Page 164
Electrical Specifications 16.16 ADC10 Characteristics Characteristic Supply voltage Absolute V = 2.2 V Supply Current DD ADLPC = 1 V < 3.6 V (3.3 V Typ) DD ADLSMP = 1 ADCO = 1 V < 5.5 V (5.0 V Typ) ...
Page 165
Characteristic 10-bit mode Differential non-linearity 8-bit mode 10-bit mode Integral non-linearity 8-bit mode 10-bit mode Zero-scale error 8-bit mode 10-bit mode Full-scale error 8-bit mode 10-bit mode Quantization error 8-bit mode 10-bit mode Input leakage error 8-bit mode (6) Bandgap ...
Page 166
Electrical Specifications 16.17 Timer Interface Module Characteristics Characteristic (1) Timer input capture pulse width Timer input capture period (1) Timer input clock pulse width 1. Values are based on characterization results, not tested in production. 2. The minimum period is ...
Page 167
Chapter 17 Ordering Information and Mechanical Specifications 17.1 Introduction This section contains ordering numbers for MC68HC08QY1, MC68HC08QY2, MC68HC08QY4, MC68HC08QT1, MC68HC08QT2, and MC69HC08QT4. In addition to package dimensions for: • 8-pin small outline integrated circuit (SOIC) package • 16-pin SOIC • ...
Page 168
...
Page 169
...
Page 170
...
Page 171
...
Page 172
...
Page 173
...
Page 174
...
Page 175
...
Page 176
... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2010. All rights reserved. ...