ad7790brm-reel Analog Devices, Inc., ad7790brm-reel Datasheet

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ad7790brm-reel

Manufacturer Part Number
ad7790brm-reel
Description
Low Power, 16-bit Buffered Sigma-delta Adc
Manufacturer
Analog Devices, Inc.
Datasheet
FEATURES
Power
RMS noise: 1.1 µV at 9.5 Hz update rate
16-bit p-p resolution
Integral nonlinearity: 3.5 ppm typical
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator
Programmable gain amplifier
Rail-to-rail input buffer
V
Temperature range: –40°C to +105°C
10-lead MSOP
INTERFACE
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Smart transmitters
Battery applications
Portable instrumentation
Sensor measurement
Temperature measurement
Pressure measurement
Weigh scales
4 to 20 mA loops
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
DD
Supply: 2.5 V to 5.25 V operation
Normal: 75 µA maximum
Power-down: 1 µA maximum
monitor channel
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD7790 is a low power, complete analog front end for
low frequency measurement applications. It contains a low
noise 16-bit ∑-∆ ADC with one differential input that can be
buffered or unbuffered along with a digital PGA, which allows
gains of 1, 2, 4, and 8.
The device operates from an internal clock. Therefore, the user
does not have to supply a clock source to the device. The output
data rate from the part is software programmable and can be
varied from 9.5 Hz to 120 Hz, with the rms noise equal to
1.1 µV at the lower update rate. The internal clock frequency
can be divided by a factor of 2, 4, or 8, which leads to a reduc-
tion in the current consumption. The update rate, cutoff
frequency, and settling time will scale with the clock frequency.
The part operates with a power supply from 2.5 V to 5.25 V.
When operating from a 3 V supply, the power dissipation for
the part is 225 µW maximum. It is housed in a 10-lead MSOP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
AIN
GND
V
Buffered Sigma-Delta ADC
DD
GND
BUF
V
DD
AD7790
© 2003 Analog Devices, Inc. All rights reserved.
16-BIT
Low Power, 16-Bit
REFIN
ADC
Figure 1.
DIGITAL
PGA
INTERFACE
INTERNAL
SERIAL
www.analog.com
CLOCK
AD7790
03538-0-001

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ad7790brm-reel Summary of contents

Page 1

... When operating from supply, the power dissipation for the part is 225 µW maximum housed in a 10-lead MSOP. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD7790 INTERNAL CLOCK SERIAL ...

Page 2

AD7790 TABLE OF CONTENTS AD7790—Specifications.................................................................. 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 On-Chip Registers .......................................................................... 10 Communications Register (RS1, RS0 = 0, 0) ......................................................................... 10 Status Register (RS1, ...

Page 3

AD7790—SPECIFICATIONS Table 2 5.25 V; REFIN(+) = 2.5 V; REFIN(–) = GND; CDIV1 = CDIV0 = 0; GND = all specifications unless otherwise noted.) MIN MAX Parameter ADC ...

Page 4

AD7790 SPECIFICATIONS (continued) Parameter REFERENCE INPUT (continued) 2 Normal Mode Rejection @ 50 Hz Common Mode Rejection @ Hz LOGIC INPUTS All Inputs Except SCLK 2 V ...

Page 5

TIMING CHARACTERISTICS Table 2 5.25 V; GND = 0 V, REFIN(+) = 2.5 V, REFIN(–) = GND, CDIV1 = CDIV0 = 0, Input Logic Input Logic ...

Page 6

AD7790 DOUT/RDY (O) I (1.6mA WITH V SINK 100µA WITH V TO OUTPUT 1.6V PIN 50pF I (200µA WITH V SOURCE 100µA WITH V Figure 2. Load Circuit for Timing Characterization CS ( MSB ...

Page 7

ABSOLUTE MAXIMUM RATINGS Table 25°C, unless otherwise noted.) A Parameter V to GND DD Analog Input Voltage to GND Reference Input Voltage to GND Total AIN/REFIN Current (Indefinite) Digital Input Voltage to GND Digital Output Voltage to ...

Page 8

AD7790 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK AD7790 AIN(+) 3 TOP VIEW 8 (Not to Scale) AIN(– REF(+) 5 6 03538-0-005 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic ...

Page 9

TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 100 FREQUENCY (Hz) Figure 6. Frequency Response for a 16.6 Hz Update Rate 3.0 2.5 2.0 1.5 1.0 0.5 ...

Page 10

AD7790 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless ...

Page 11

STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0x88) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation read, ...

Page 12

AD7790 Bit Location Bit Name Description MR2 0 This bit must be programmed with a Logic 0 for correct operation. MR1 BUF Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in unbuffered mode, ...

Page 13

ADC CIRCUIT INFORMATION OVERVIEW The AD7790 is a low power ADC that incorporates a ∑-∆ modulator, a buffer, a PGA, and on-chip digital filtering intend- ed for the measurement of wide dynamic range, low frequency signals such as those in ...

Page 14

AD7790 DIGITAL INTERFACE As previously outlined, the AD7790’s programmable functions are controlled using a set of on-chip registers. Data is written to these registers via the part’s serial interface and read access to the on-chip registers is also provided by ...

Page 15

Single Conversion Mode In single conversion mode, the AD7790 is placed in shutdown mode between conversions. When a single conversion is initi- ated by setting MD1 to 1 and MD0 the mode register, the AD7790 powers up, ...

Page 16

AD7790 Continuous Read Mode Rather than write to the communications register each time a conversion is complete to access the data, the AD7790 can be placed in continuous read mode. By writing 001111XX to the communications register, the user only ...

Page 17

CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL The AD7790 has one differential analog input channel. This is connected to the on-chip buffer amplifier when the device is operated in buffered mode and directly to the modulator when the device is operated in ...

Page 18

AD7790 REFIN(+) without introducing gain errors in the system. Deriv- ing the reference input voltage across an external resistor will mean that the reference input sees a significant external source impedance. External decoupling on the REFIN pins would not be ...

Page 19

... ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Table 17. Ordering Guide Model Temperature Range AD7790BRM –40°C to +105°C AD7790BRM-REEL –40°C to +105°C 3.00 BSC 10 6 4.90 BSC 3.00 BSC 1 ...

Page 20

... AD7790 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective companies. C03538-0-8/03(0) Rev Page ...

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