ad7450ar-reel7 Analog Devices, Inc., ad7450ar-reel7 Datasheet - Page 15

• Manufacturer Part Number: ad7450ar-reel7
• Description: Differential Input, 1 Msps 12-bit Adc In
  soic-8 And So-8
• Manufacturer: Analog Devices, Inc.

SINGLE-ENDED OPERATION
When supplied with a 5 V power supply, the AD7450 can handle
a single-ended input. The design of this part is optimized for
differential operation, so with a single-ended input, performance
will degrade. Linearity will typically degrade by 0.2 LSBs, zero
code and full-scale errors will typically degrade by 2 LSBs, and
ac performance is not guaranteed.
To operate the AD7450 in single-ended mode, the V
coupled to the signal source, while the V
appropriate voltage corresponding to the midscale code transi-
tion. This voltage is the common mode, which is a fixed dc
voltage (usually the reference). The V
this value and should have voltage span of 2
of the full dynamic range of the part. Therefore, the input signal
will have peak-to-peak values of common mode ± V
analog input is unipolar then an op amp in a noninverting unity
gain configuration can be used to drive the V
the ADC operates from a single supply, it is necessary to level
shift ground based bipolar signals to comply with the input
requirements. An op amp can be configured to rescale and level
shift the ground based bipolar signal so it is compatible with the
selected input range of the AD7450 (see Figure 18).
SERIAL INTERFACE
Figure 19 shows a detailed timing diagram for the serial interface
of the AD7450. The serial clock provides the conversion clock
and also controls the transfer of data from the AD7450 during
conversion. CS initiates the conversion process and frames the
data transfer. The falling edge of CS puts the track-and-hold into
hold mode and takes the bus out of three-state. The analog input
is sampled and the conversion initiated at this point. The
conversion will require 16 SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track-and-hold
will go back into track on the next SCLK rising edge as shown
at Point B in Figure 19. On the 16th SCLK falling edge, the
SDATA line will go back into three-state.
If the rising edge of CS occurs before 16 SCLKs have elapsed,
the conversion will be terminated, and the SDATA line will go
back into three-state. Sixteen serial clock cycles are required to
perform a conversion and to access data from the AD7450. CS
going low provides the first leading zero to be read in by the
microcontroller or DSP. The remaining data is then clocked out
on the subsequent SCLK falling edges beginning with the second
leading zero. Thus, the first falling clock edge on the serial clock
provides the second leading zero. The final bit in the data transfer
REV. 0
+2.5V
–2.5V
Figure 18. Applying a Bipolar Single-Ended
Input to the AD7450
0V
V
IN
R
R
R
EXTERNAL
V
REF
+
–
(2.5V)
R
IN+
2.5V
0.1 F
IN–
5V
0V
input swings around
input is biased to the
IN+
V
V
V
IN+
IN–
pin. Because
REF
AD7450
REF
to make use
IN+
V
. If the
REF
input is
–15–
is valid on the 16th falling edge, having been clocked out on the
previous (15th) falling edge. Once the conversion is complete
and the data has been accessed after the 16 clock cycles, it is
important to ensure that before the next conversion is initiated,
enough time is left to meet the acquisition and quiet time speci-
fications (see timing examples). To achieve 1 MSPS with an 18
MHz clock for V
conversion and leave enough time before the next conversion for
the acquisition and quiet time. This is the same for achieving
833 kSPS with a 15 MHz clock for V
In applications with a slower SCLK, it may be possible to read
in data on each SCLK rising edge, i.e., the first rising edge of
SCLK after the CS falling edge would have the leading zero
provided and the 15th SCLK edge would have DB0 provided.
Timing Example 1
Having f
a cycle time of:
A cycle consists of:
Therefore, if t
This 296 ns satisfies the requirement of 200 ns for t
Figure 20, t
where t
fying the minimum requirement of 25 ns.
Timing Example 2
Having f
a cycle time of:
A cycle consists of:
Therefore if t
This 664 ns satisfies the requirement of 200 ns for t
Figure 20, t
where t
fying the minimum requirement of 25 ns.
As in this example and with other slower clock values, the signal
may already be acquired before the conversion is complete, but it
is still necessary to leave 25 ns minimum t
sions. In Timing Example 2, the signal should be fully acquired
at approximately Point C in Figure 20.
1
10
1
10
t
t
2
t
t
2
2
2
ACQ
ACQ
.5 1 f
.5 1 f
Throughput
Throughput
+
+
ns
ns
(
(
12 5 1
12 5 1
8
8
= 296
= 664
SCLK
+
SCLK
+
= 35 ns. This allows a value of 122 ns for t
= 35 ns. This allows a value of 129 ns for t
.
.
12 5 1 18
12 5 1 5
SCLK
SCLK
ACQ
ACQ
(
(
.
.
2
= 18 MHz and a throughput rate of 1 MSPS gives
= 5 MHz and a throughput rate of 315 kSPS gives
2
ns
ns
is 10 ns then:
f
f
= 10 ns then:
)
)
(
(
SCLK
SCLK
is comprised of:
is comprised of:
+
+
DD
=
=
1 1 000 000 1
1 315 000 3 174
t
t
8
8
MHz
= 5 V, an 18 clock burst will perform the
)
)
MHz
+
+
,
+
+
t
t
t
QUIET
t
QUIET
,
ACQ
ACQ
)
,
)
+
+
=
=
t
=
ACQ
t
1
ACQ
3 174
=
.
µs
.
=
µ
=
3 174
s
DD
1
µs
.
µ
µ
s
= 3 V.
s
QUIET
µ
s
AD7450
between conver-
QUIET
QUIET
ACQ
ACQ
. From
. From
, satis-
, satis-