ad73322l Analog Devices, Inc., ad73322l Datasheet
ad73322l
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ad73322l Summary of contents
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... This is featured on both codecs and can be used for impedance matching or scaling when interfacing to subscriber line interface circuits (SLICs). The AD73322L is particularly suitable for a variety of appli- cations in the speech and telephony area, including low bit rate, high quality compression, speech enhancement, recognition, and synthesis ...
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... Control Register B...................................................................... 21 Control Register C...................................................................... 21 Control Register D ..................................................................... 22 Control Register E ...................................................................... 22 Control Register F ...................................................................... 22 Control Register G ..................................................................... 23 Control Register H ..................................................................... 23 Operation......................................................................................... 24 Resetting the AD73322L ........................................................... 24 Power Management ................................................................... 24 Operating Modes........................................................................ 24 Program (Control) Mode .......................................................... 24 Data Mode................................................................................... 25 Mixed Program/Data Mode...................................................... 25 Digital Loop-Back Mode........................................................... 25 SPORT Loop-Back Mode.......................................................... 25 Analog Loop-Back Mode ...
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... Updated Outline Dimensions........................................................46 Changes to Ordering Guide...........................................................47 4/01—Revision 0: Initial Version Mixed-Mode Operation.............................................................37 Interrupts .....................................................................................37 Initialization.................................................................................38 Running the AD73322L with ADCs or DACs in Power-Down .......................................................................................................38 DAC Timing Control Example .....................................................40 Configuring an AD73322L to Operate in Data Mode ...............41 Configuring an AD73322L to Operate in Mixed Mode ............43 Outline Dimensions........................................................................46 Ordering Guide ...........................................................................47 Rev Page AD73322L ...
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... AD73322L SPECIFICATIONS AVDD = 3 V ± 10%; DVDD = 3 V ± 10%; DGND = AGND = unless otherwise noted. Operating temperature range as follows: A grade, T Table 1. Parameter REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, V REFOUT Minimum Load Resistance Maximum Load Capacitance INPUT AMPLIFIER ...
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... Rev Page AD73322L Test Conditions/Comments Input amplifiers bypassed Tested to 5 MSB of settings Includes DAC delay Tap gain change from −FS to +FS; includes DAC settling time DAC unloaded PGA = 6 dB Max output = (1.578/1.2) × VREFCAP PGA = 6 dB Max output = 2 × ...
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... AD73322L Parameter 0.0625 0.125 0.1875 0.25 0.3125 0.375 0.4375 > 0.5 LOGIC INPUTS V , Input High Voltage INH V , Input Low Voltage INL I , Input Current Input Capacitance IN LOGIC OUTPUT V , Output High Voltage Output Low Voltage OL Three-State Leakage Current POWER SUPPLIES AVDD1, AVDD2 9 DVDD Test conditions: input PGA set for 0 dB gain, output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted) ...
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... SDI/SDIFS setup before SCLK low ns min SDI/SDIFS hold after SCLK low ns max SDOFS delay from SCLK high ns min SDOFS hold after SCLK high ns min SDO hold after SCLK high ns max SDO delay from SCLK high ns max SCLK delay from MCLK Rev Page AD73322L ...
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... AD73322L TIMING DIAGRAMS SE (I) THREE- STATE SCLK (O) SDIFS (I) SDI ( THREE- STATE SDOFS (O) THREE- STATE SDO ( Figure 2. MCLK Timing 100µ OUTPUT PIN C L 15pF 100µ Figure 3. Load Circuit for Timing Specifications MCLK ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev Page AD73322L ...
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... CONNECT Figure 8. 44-Lead Plastic Thin Quad Flatpack Rev Page VINP1 1 28 VFBN2 VFBP1 2 VINN2 27 VINN1 3 26 VFBP2 VFBN1 4 25 VINP2 AD73322L REFOUT 5 24 VOUTN1 TOP VIEW REFCAP 6 23 VOUTP1 AVDD2 7 22 VOUTN2 AGND2 8 21 VOUTP2 DGND AVDD1 ...
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... Analog Input to the inverting input amplifier on Channel 2’s negative input. VFBN2 Feedback connection from the output of the inverting amplifier on Channel 2’s negative input. When the input amplifiers are bypassed, this pin allows direct access to the negative input of Channel 2’s sigma-delta modulator. Rev Page AD73322L ...
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... Analog loop-back. BW Bandwidth. CRx A control register where placeholder for an alphabetic character (A to H). There are eight read/write control registers on the AD73322L— CRA through CRH. CRx:n A bit position, where placeholder for a numeric character (0 to 7), within a control register, where placeholder for an alphabetic character ( ...
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... Hz to 3.4 kHz) DVDD DIGITAL Σ-∆ DECIMATOR MODULATOR GAIN ±1 DIGITAL INTER- Σ-∆ POLATOR MODULATOR SERIAL I/O PORT DIGITAL Σ-∆ DECIMATOR MODULATOR GAIN ±1 DIGITAL INTER- Σ-∆ POLATOR MODULATOR DGND AD73322L –15 –5 5 3.17 SDI SDIFS SCLK RESET MCLK SE SDO SDOFS ...
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... Sigma-delta converters employ a technique known as oversampling, where the sampling rate is many times the highest frequency of interest. In the case of the AD73322L, the initial sampling rate of the sigma-delta modulator is DMCLK/8. The main effect of oversampling is that the quantization noise is spread over a very wide bandwidth (Figure 13) ...
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... SRNAL SINTER Figure 16. Final Filter (HPF) Transfer Function DECIMATION FILTER The digital filter used in the AD73322L carries out two important functions. First, it removes the out-of-band quantization noise, which is shaped by the analog modulator and second, it decimates the high frequency bit stream to a lower rate, 16-bit word ...
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... MUTE bit (CRD:7) in Control Register D. The output signal is dc-biased to the codec’s on-chip voltage reference. VOLTAGE REFERENCE The AD73322L reference, REFCAP band gap reference that provides a low noise, temperature-compensated reference to the DAC and ADC. A buffered version of the reference is also made available on the REFOUT pin, and can be used to bias other external analog circuitry ...
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... CONTROL REGISTER 1H ANALOG AND DIGITAL GAIN TAPS The AD73322L features analog and digital feedback paths between input and output. The amount of feedback is deter- mined by the gain setting which is programmed in the control registers. This feature can typically be used for balancing the effective impedance between input and output when used in subscriber line interface circuit (SLIC) interfacing ...
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... Due to the fact that the SPORT of each codec block uses a common serial register for serial input and output, commun- ications between an AD73322L codec and a host processor (DSP engine) must always be initiated by the codecs themselves. In this configuration, the codecs are described as being in master mode ...
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... Codecs 1 and 2, including the eight control registers (A–H), external MCLK to internal DMCLK divider, and serial clock divider. The divider rates are controlled by the setting of Control Register B. The AD73322L features a master clock divider that allows users the flexibility of dividing externally available high frequency DSP or CPU clocks to ...
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... Bits Register Address This 3-bit field is used to select one of the eight control registers on the AD73322L. Bits Register Data This 8-bit field holds the data that written to or read from the selected register provided the address field is zero ...
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... SPORT Loop-Back Mode (0 = off enabled) Device Count (Bit 0) Device Count (Bit 1) Device Count (Bit 2) Software Reset (0 = off initiates reset MCD0 SCD1 4 3 PUDAC PUADC Rev Page BLB MM DATA/PGM 2 1 SCD0 DIR1 2 1 PUIA PUAGT AD73322L 0 DIR0 0 PU ...
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... AD73322L CONTROL REGISTER D Table 21. Control Register D Description MUTE OGS2 OGS1 Bit Name Description 0 IGS0 Input Gain Select (Bit 0) 1 IGS1 Input Gain Select (Bit 1) 2 IGS2 Input Gain Select (Bit 2) 3 RMOD Reset ADC Modulator (0 = off reset enabled) 4 OGS0 Output Gain Select (Bit 0) ...
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... Digital Gain Tap Coefficient (Bit 9) Digital Gain Tap Coefficient (Bit 10) Digital Gain Tap Coefficient (Bit 11) Digital Gain Tap Coefficient (Bit 12) Digital Gain Tap Coefficient (Bit 13) Digital Gain Tap Coefficient (Bit 14) Digital Gain Tap Coefficient (Bit 15) Rev Page AD73322L DGTC2 DGTC1 DGTC0 2 ...
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... DAC data to the device(s). As the AD73322L is a dual codec, it features two separate device addresses for programming purposes. If the AD73322L is used in a standalone configuration connected to a DSP, the two device addresses correspond to 0 and 1 ...
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... DAC update. Also, as the device count setting defaults must be set to 2 (001b) to ensure correct update of both DACs on the AD73322L. The section DAC Timing Control Example details the initial- ization and operation of an AD73322L in normal data mode. SE SCLK SDOFS ...
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... VINP1 VFBP1 VOUTP1 VOUTN1 REFOUT REFCAP ANALOG INVERTING LOOP-BACK OP AMPS INVERT SELECT V REF GAIN ±1 CONTINUOUS TIME +6/–15dB LOW-PASS PGA FILTER REFERENCE Figure 22. Analog Loop-Back Connectivity Rev Page SINGLE- ENDED ENABLE 0/38dB PGA V REF ANALOG GAIN TAP POWERED DOWN AD73322L ...
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... INTERFACING The AD73322L can be interfaced to most modern DSP engines using conventional serial port connections and an extra enable control line. Both serial input and output data use an accom- panying frame synchronization signal that is active high one clock cycle before the start of the 16-bit word or during the last bit of the previous word if transmission is continuous ...
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... The interrupt latency will include the time between the ADC sampling event and the Rx interrupt being generated in the DSP—this should be 16 SCLK cycles. Because the AD73322L is configured in cascade mode, each device must know the number of devices in the cascade because the data and mixed modes use a method of counting input frame sync pulses to decide when they should update the DAC register from the serial input register ...
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... Figure 26 shows the resulting spectrum following the filtering and decimation of the spectrum of Figure 25 from 64 kHz kHz rate. The AD73322L also features direct sampling at the lower rate of 8 kHz. This is achieved by the use of extended decimation registers within the decimator block, which allows for the increased word growth associated with the higher effective oversampling ratio ...
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... FREQUENCY (Hz) Figure 29. FFT (ADC 8 kHz Filtered and Decimated from 16 kHz) ENCODER GROUP DELAY When programmed for high sampling rates, the AD73322L offers a very low level of group delay, which is given by Group Delay (Decimator) = Order × ((M − 1)/2) × T where: Order is the order of the decimator (= 3) ...
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... Because the AD73322L can be operated at 8 kHz (see Figure 31 kHz sampling rates, which make it particularly suited for voice-band processing, the user must understand the action of the interpolator’s sinc3 response. As was the case with the encoder section, if the output signal’s frequency response is not ...
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... AD73322L are specifically designed FILTER to interface to the ADC’s SC input stage. The AD73322L’s on-chip 38 dB preamplifier can be enabled when there is not enough gain in the input circuit; the pre- AD73322L amplifier is configured by bits IGS0-2 of CRD. The total gain ...
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... If the ADC is being connected in single-ended mode, the AD73322L should be programmed for single-ended mode using the SEEN and INV bits of CRF and the inputs connected as shown in Figure 37. When operated in single-ended input mode, the AD73322L can multiplex one of the two inputs to the ADC input. 0.1µF 10kΩ ...
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... In this circuit, the AD73322L input channel is being used in single-ended mode where the internal inverting amplifier provides suitable gain to scale the input signal relative to the ADC’s full-scale input range ...
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... TIME LOW-PASS Where it is required to configure a cascade eight codecs FILTER (four AD73322L dual codecs), ensure that the timing of the SE and RESET signals is synchronized at each device in the cascade. A simple D-type flip-flop is sufficient to sync each AD73322L signal to the master clock MCLK Figure 45. ...
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... The digital filters also remove noise from the analog inputs provided the noise source does not saturate the analog modulator. However, because the resolution of the AD73322L’s ADC is high, and the noise levels from the AD73322L are so low, care must be taken with regard to grounding and layout. TFS ...
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... DSP SOFTWARE CONSIDERATIONS WHEN INTERFACING TO THE AD73322L When choosing the operating mode and hardware config- uration of the AD73322L, be aware of their implications for DSP software operation. The user has the flexibility of choosing from either FSLB or nonFSLB when deciding on DSP-to-AFE connectivity. There is also a choice to be made between using autobuffering of input and output samples, or simply choosing to accept them as individual interrupts ...
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... In FSLB configurations, a single control word per codec per sample period is sent to the AD73322L. In nonFSLB possible to initialize the device in a single sample period provided the SCLK rate is programmed to a high rate also ...
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... At each occurrence of an SDOFS pulse, the DSP’s transmit buffer contents are sent to the SDI pin of the AD73322L. This also causes a subsequent DSP Tx interrupt which transfers the initialization word, pointed to by the circular buffer pointer, to the Tx buffer. The buffer pointer is updated to point to the next unsent initialization word ...
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... DATA REGISTER UPDATE DAC LOAD FROM DAC REGISTER the AD73322L. Time t sending the DAC word to the AD73322L. This sequence ends at time t the AD73322L’s serial register. However, the DAC is not updated from the DAC register until time t , the SDOFS is raised accept-able in certain applications. In order to reduce this delay ...
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... CONFIGURING AN AD73322L TO OPERATE IN DATA MODE This section describes the typical sequence of control words that are required to be sent to an AD73322L to set it up for data 1 mode operation. In this sequence, Registers B, C, and A are programmed before the device enters data mode. This description refers to the steps in Table 27. ...
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... DAC WORD CH 1 -> 1000000000000000 12 At this time, the DAC of both Channel 1 and Channel 2 is updated and the ADC of both Channel 1 and Channel 2 has been read. AD73322L Channel 1 AD73322L Channel 2 Data-word OUTPUT CH1 -> Data-word OUTPUT CH2 -> 0000000000000000 0000000000000000 Control Word CRB–CH2 -> ...
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... Steps detail an ADC and DAC update cycle using the nonFSLB configuration. In this case, no control register update is required. 1 Channel 1 and Channel 2 refer to the two AFE sections of the AD73322L. 2 This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are enabled. Ensure there is no latency (separation) between control words in a cascade configuration ...
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... The ADC data from both channels has been read, Control Register C of both channels has been programmed, and DAC data for CRC-CH2 -> 11001010xxxxxxxx 21 CRC-CH1 -> 10000010xxxxxxxx 22 23 AD73322L Channel 1 AD73322L Channel 2 OUTPUT CH1 -> OUTPUT CH2 -> 0000000000000000 0000000000000000 OUTPUT CH1 -> 0000000000000000 CRA-CH2 -> 1000100000010011 CRA-CH1 CRA-CH2 1000000000010011 1000000000010011 Control Register A of both channels has been programmed ...
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... DAC WORD CH 2 -> 0111111111111111 29 DAC WORD CH 1 -> 1000000000000000 30 The ADC data from both channels has been read, and the DAC data for both channels has been written. AD73322L Channel 1 AD73322L Channel 2 READBACK CH 1 -> 1111101011111001 ADC RESULT CH1 -> ADC RESULT CH2 -> Unknown Data Unknown Data ADC RESULT CH1 -> ...
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... AD73322L OUTLINE DIMENSIONS 18.10 (0.7126) 17.70 (0.6969 7.60 (0.2992) 7.40 (0.2913 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) 1.27 (0.0500) SEATING 0.51 (0.0201) COPLANARITY BSC PLANE 0.31 (0.0122) 0.10 COMPLIANT TO JEDEC STANDARDS MS-013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 49 ...
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... AD73322LAST-REEL −40°C to +85°C AD73322LYR −40°C to +105°C AD73322LYR-REEL −40°C to +105°C AD73322LYR-REEL7 −40°C to +105°C AD73322LYRU −40°C to +105°C AD73322LYRU-REEL −40°C to +105°C AD73322LYST −40°C to +105°C AD73322LYST-REEL −40°C to +105° Pb-free part ...
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... AD73322L NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00691–0–12/04(A) Rev Page ...