ad73322arz-reel7 Analog Devices, Inc., ad73322arz-reel7 Datasheet
ad73322arz-reel7
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ad73322arz-reel7 Summary of contents
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... The AD73322 is available in 28-lead SOIC and 44-lead LQFP packages. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 AD73322 DVDD AD73322 SDI SDIFS SCLK SE SPORT RESET MCLK SDOFS SDO AGND2 DGND World Wide Web Site: http://www.analog.com © Analog Devices, Inc., 2000 ...
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AD73322–SPECIFICATIONS Parameter REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, V REFOUT Minimum Load Resistance Maximum Load Capacitance INPUT AMPLIFIER Offset Maximum Output Swing Feedback Resistance Feedback Capacitance ANALOG GAIN TAP Gain at Maximum Setting ...
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Parameter DAC SPECIFICATIONS 2 Maximum Voltage Output Swing Single-Ended Differential Nominal Voltage Output Swing (0 dBm0) Single-Ended Differential Output Bias Voltage Absolute Gain Gain Tracking Error Signal to (Noise + Distortion dBm0 PGA = 6 dB Total Harmonic ...
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AD73322 Parameter LOGIC INPUTS V , Input High Voltage INH V , Input Low Voltage INL I , Input Current Input Capacitance IN LOGIC OUTPUT V , Output High Voltage Output Low Voltage OL ...
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V SPECIFICATIONS Parameter REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, VREFOUT Minimum Load Resistance Maximum Load Capacitance INPUT AMPLIFIER Offset Maximum Output Swing Feedback Resistance Feedback ...
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AD73322 P arameter DIGITAL GAIN TAP Gain at Maximum Setting Gain at Minimum Setting Gain Resolution Delay Settling Time DAC SPECIFICATIONS 2 Maximum Voltage Output Swing Single-Ended Differential Nominal Voltage Output Swing (0 dBm0) Single-Ended Differential Output Bias Voltage Absolute ...
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Parameter LOGIC INPUTS V , Input High Voltage INH V , Input Low Voltage INL I , Input Current Input Capacitance IN LOGIC OUTPUT V , Output High Voltage Output Low Voltage OL Three-State ...
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AD73322 VREFCAP VREFOUT ADC Maximum Input Range Nominal Reference Level DAC Maximum Voltage Output Swing Single-Ended Differential Nominal Voltage Output Swing Single-Ended Differential Output Bias Voltage TIMING CHARACTERISTICS Limit at Parameter T = – +85 ...
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TIMING CHARACTERISTICS Limit at Parameter T = – + Clock Signals 24 24.4 3 Serial Port 0 0 ...
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AD73322 ABSOLUTE MAXIMUM RATINGS +25 C unless otherwise noted) A AVDD, DVDD to GND . . . . . . . . . . . . . . . . . –0 AGND to ...
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Mnemonic Function VINP1 Analog Input to the inverting input amplifier on Channel 1’s positive input. VFBP1 Feedback Connection from the output of the inverting amplifier on Channel 1’s positive input. When the input amplifiers are bypassed, this pin allows direct ...
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AD73322 TERMINOLOGY Absolute Gain Absolute gain is a measure of converter gain for a known signal. Absolute gain is measured (differentially) with a 1 kHz sine wave at 0 dBm0 for the DAC and with a 1 kHz sine wave ...
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Typical Performance Characteristics –10 –85 –75 –65 –55 –45 –35 V – dBm0 IN Figure 5. S/(N+D) vs. V (ADC @ 3 V) over Voiceband IN Bandwidth (300 Hz–3.4 kHz) 80 ...
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AD73322 VFBN1 VINN1 ANALOG V LOOP REF BACK VINP1 VFBP1 VOUTP1 CONTINUOUS +6/–15dB PGA VOUTN1 REFCAP REFERENCE REFOUT VFBN2 VINN2 ANALOG V LOOP REF BACK VINP2 VFBP2 VOUTP2 CONTINUOUS +6/–15dB PGA VOUTN2 AGND1 FUNCTIONAL DESCRIPTION Encoder Channels Both encoder channels ...
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ADC Both ADCs consist of an analog sigma-delta modulator and a digital antialiasing decimation filter. The sigma-delta modu- lator noise-shapes the signal and produces 1-bit samples at a DMCLK/8 rate. This bitstream, representing the analog input signal, is input to ...
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AD73322 Decimation Filter The digital filter used in the AD73322 carries out two important functions. Firstly, it removes the out-of-band quantization noise, which is shaped by the analog modulator and secondly, it decimates the high frequency bit-stream to a lower ...
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Differential Output Amplifiers The decoder has a differential analog output pair (VOUTP and VOUTN). The output channel can be muted by setting the MUTE bit (CRD:7) in Control Register D. The output signal is dc-biased to the codec’s on-chip voltage ...
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AD73322 Table VI. Analog Gain Tap Settings* AGTC4 AGTC3 AGTC2 AGTC1 – – – – ...
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The SPORT can work at four different serial clock (SCLK) rates: chosen from DMCLK, DMCLK/2, DMCLK/4 or DMCLK/8, where DMCLK is the internal or device master clock resulting from the external or pin master clock being divided by the master ...
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AD73322 Address (Binary) Name 000 CRA 001 CRB 010 CRC 011 CRD 100 CRE 101 CRF 110 CRG 111 CRH C/D R/W Device Address Control Frame Bit 15 Control/Data Bit 14 Read/Write Bits 13–11 Device ...
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CONTROL REGISTER Bit CONTROL REGISTER B CEE Bit CONTROL REGISTER C 5VEN Bit ...
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AD73322 CONTROL REGISTER D MUTE Bit CONTROL REGISTER E Bit CONTROL REGISTER F ALB/ AGTM Bit ...
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CONTROL REGISTER G 7 DGTC7 Bit CONTROL REGISTER H 7 DGTC15 DGTC14 DGTC13 DGTC12 DGTC11 DGTC10 DGTC9 Bit REV. B Table XX. Control Register ...
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AD73322 OPERATION Resetting the AD73322 The RESET pin resets all the control registers. All registers are reset to zero, indicating that the default SCLK rate (DMCLK/ 8) and sample rate (DMCLK/2048) are at a minimum to ensure that slow speed ...
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In a single AD73322 configuration, each 16-bit data frame sent from the DSP to the device is interpreted as DAC data, but it is necessary to send two DAC words per sample period in order to ensure DAC update. Also, ...
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AD73322 INTERFACING The AD73322 can be interfaced to most modern DSP engines using conventional serial port connections and an extra enable control line. Both serial input and output data use an accompa- nying frame synchronization signal that is active high ...
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Table XXII. Device Count Settings DC2 DC1 DC0 PERFORMANCE As the AD73322 is designed to provide ...
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AD73322 The device features an on-chip master clock divider circuit that allows the sample rate to be reduced as the sampling rate of the sigma-delta converter is proportional to the output of the MCLK Divider (whose default state is divide ...
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As the AD73322 can be operated at 8 kHz (see Figure 26 kHz sampling rates, which make it particularly suited for voiceband processing important to understand the action of the interpolator’s Sinc3 response. As was the ...
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AD73322 DESIGN CONSIDERATIONS The AD73322 features both differential inputs and outputs on each channel to provide optimal performance and avoid com- mon mode noise also possible to interface either inputs or outputs in single-ended mode. This section details ...
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The AD73322’s ADC inputs are biased about the internal refer- ence level (REFCAP level), therefore it may be necessary to bias external signals to this level using the buffered REFOUT level as the reference. This is applicable in either dc- ...
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AD73322 Interfacing to an Electret Microphone Figure 34 details an interface for an electret microphone which may be used in some voice applications. Electret microphones typically feature a FET amplifier whose output is accessed on the same lead which supplies ...
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Digital Interfacing The AD73322 is designed to easily interface to most common DSPs. The SCLK, SDO, SDOFS, SDI and SDIFS must be connected to the DSP’s Serial Clock, Receive Data, Receive Data Frame Sync, Transmit Data and Transmit Data Frame ...
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AD73322 Grounding and Layout Since the analog inputs to the AD73322 are differential, most of the voltages in the analog modulator are common-mode volt- ages. The excellent common-mode rejection of the part will remove common-mode noise on these inputs. The ...
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DSP SOFTWARE CONSIDERATIONS WHEN INTERFACING TO THE AD73322 It is important when choosing the operating mode and hardware configuration of the AD73322 to be aware of their implications for DSP software operation. The user has the flexibility of choosing from ...
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AD73322 The circular buffer approach can be useful if a long initialization sequence is required. The list of initialization words is put into the buffer in the required order. .VAR/DM/RAM/CIRC init_cmds[16]; {Codec init sequence} .VAR/DM/RAM stat_flag; .INIT init_cmds ...
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APPENDIX A DAC Timing Control Example The AD73322’s DAC is loaded from the DAC register contents just before the ADC register contents are loaded to the serial register (SDOFS going high). This default DAC load position can be advanced in ...
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AD73322 APPENDIX B Configuring an AD73322 to Operate in Data Mode This section describes the typical sequence of control words that are required to be sent to an AD73322 to set it up for data mode operation. In this sequence ...
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DSP Step Tx 1 CRB–CH2 1000100100001011 2 CRB–CH1 1000000100001011 3 CRC–CH2 1000101011111001 4 CRC–CH2 1000101011111001 5 CRC–CH1 1000001011111001 6 CRA–CH2 1000100000010001 7 CRA–CH2 1000100000010001 8 CRA–CH1 1000000000010001 9 CRB-CH2 0111111111111111 10 DAC WORD CH 2 0111111111111111 11 DAC WORD CH ...
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AD73322 APPENDIX C Configuring an AD73322 to Operate in Mixed Mode This section describes a typical sequence of control words that would be sent to an AD73322 to configure it for operation in mixed mode not intended to ...
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DSP Step Tx DON’T CARE 1 xxxxxxxxxxxxxxxx DON’T CARE 2 xxxxxxxxxxxxxxxx CRA-CH2 3 1000101011111001 CRA-CH1 4 1000000000010011 DON’T CARE 5 xxxxxxxxxxxxxxxx DON’T CARE 6 xxxxxxxxxxxxxxxx DON’T CARE 7 xxxxxxxxxxxxxxxx CRB-CH2 8 1000100100001011 CRB-CH1 9 1000000100001011 DON’T CARE 10 xxxxxxxxxxxxxxxx DON’T ...
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AD73322 Topic FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SEATING 0.004 (0.10) 0.006 (0.15) 0.002 (0.05) REV. B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Wide Body SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70 PIN 1 ...