ad73311

Manufacturer Part Numberad73311
DescriptionLow Cost, Low Power Cmos General Purpose Analog Front End
ManufacturerAnalog Devices, Inc.
ad73311 datasheet
 
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a
AVDD1
VINP
0/38dB
PGA
VINN
VOUTP
CONTINUOUS
+6/–15dB
TIME
PGA
LOW-PASS FILTER
VOUTN
REFCAP
REFERENCE
REFOUT
AGND1
Low Cost, Low Power CMOS
General Purpose Analog Front End
GENERAL DESCRIPTION
The AD73311 is a complete front-end processor for general
purpose applications including speech and telephony. It features
a 16-bit A/D conversion channel and a 16-bit D/A conversion
channel. Each channel provides 70 dB signal-to-noise ratio over
a voiceband signal bandwidth. The final channel bandwidth can
be reduced, and signal-to-noise ratio improved, by external
digital filtering in a DSP engine.
The AD73311 is suitable for a variety of applications in the
speech and telephony area including low bit rate, high quality
compression, speech enhancement, recognition and synthesis.
The low group delay characteristic of the part makes it suitable
for single or multichannel active control applications.
The gains of the A/D and D/A conversion channels are pro-
grammable over 38 dB and 21 dB ranges respectively. An
on-chip reference voltage is included to allow single supply
operation. A serial port (SPORT) allows easy interfacing of
single or cascaded devices to industry standard DSP engines.
The AD73311 is available in both 20-lead SOIC and SSOP
packages.
FUNCTIONAL BLOCK DIAGRAM
AVDD2
ANALOG
SIGMA-DELTA
MODULATOR
SWITCHED-
DIGITAL
1-BIT
CAPACITOR
SIGMA-DELTA
DAC
LOW-PASS FILTER
MODULATOR
AD73311
AGND2
AD73311
DVDD
SDI
SDIFS
DECIMATOR
SCLK
SERIAL
SDO
I/O
PORT
SDOFS
SE
INTERPOLATOR
MCLK
RESET
DGND

ad73311 Summary of contents

  • Page 1

    ... The final channel bandwidth can be reduced, and signal-to-noise ratio improved, by external digital filtering in a DSP engine. The AD73311 is suitable for a variety of applications in the speech and telephony area including low bit rate, high quality compression, speech enhancement, recognition and synthesis. ...

  • Page 2

    ... PGA = 6 dB Total Harmonic Distortion PGA = 0 dB PGA = 6 dB Intermodulation Distortion Idle Channel Noise Crosstalk 1 (AVDD = +3 V 10%; DVDD = + kHz unless otherwise noted MIN MAX AD73311A Min Typ Max Unit 1.08 1.2 1. ppm/°C Ω 68 1.08 1.2 1. kΩ ...

  • Page 3

    ... AD73311 Test Conditions/Comments Input Signal Level at AVDD and DVDD Pins: 1.0 kHz, 100 mV p-p Sine Wave 64 kHz Input Sample Rate, Interpolator Bypassed (CRE PGA = 6 dB Channel Frequency Response Is Programmable by Means of External Digital Filtering |IOUT| ≤ 100 µA |IOUT| ≤ 100 µA ...

  • Page 4

    ... PGA = 6 dB Total Harmonic Distortion PGA = 0 dB PGA = 6 dB Intermodulation Distortion Idle Channel Noise Crosstalk 1 (AVDD = +5 V 10%; DVDD = + kHz unless otherwise noted MIN MAX AD73311A Min Typ Max Unit 1 ppm/°C Ω 68 1 kΩ ...

  • Page 5

    ... V 4.5 5 –40°C and T = +85°C. MIN MAX 11 )/DMCLK. AD73311 Test Conditions/Comments Input Signal Level at AVDD and DVDD Pins: 1.0 kHz, 100 mV p-p Sine Wave 64 kHz Input Sample Rate, Interpolator Bypassed (CRE PGA = 6 dB Channel Frequency Response Is Programmable by Means of External Digital Filtering | < 100 µA ...

  • Page 6

    ... AD73311 Table II. Current Summary (AVDD = DVDD = +5.5 V) Analog Internal Digital External Interface Conditions Current Current ADC On Only 8.5 6 ADC and DAC On 14.5 6 REFCAP On Only 0.8 0 REFCAP and REFOUT On Only 3.5 0 All Sections Off 0 1.5 All Sections Off 0 0.01 The above values are in mA and are typical values unless otherwise noted. ...

  • Page 7

    ... MCLK SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE). AD73311 10%; AGND = DGND = MlN MAX Description See Figure 1 MCLK Period MCLK Width High MCLK Width Low See Figures 3 and 4 SCLK Period SCLK Width High SCLK Width Low ...

  • Page 8

    ... AD73311 SE (I) THREE- STATE SCLK (O) SDIFS (I) SDI (I) THREE STATE SDOFS (O) THREE- STATE SDO ( –10 –85 –75 –65 –55 –45 –35 V – dBm0 –10 –85 –75 –65 –55 –45 –35 V – dBm0 ...

  • Page 9

    ... The upgrade consists of a replacement PROM and connector. This option is intended for existing owners of EZ-KIT Lite. 4 The EZ-KIT Lite has been modified to allow it to interface with the AD73311 evaluation board. This option is intended for users who do not already have an EZ-KIT Lite. ...

  • Page 10

    ... AD73311 Pin Number Mnemonic Function 1 VOUTP Analog Output from the Positive Terminal of the Output Channel. 2 VOUTN Analog Output from the Negative Terminal of the Output Channel. 3 AVDD1 Analog Power Supply Connection for the Output Driver. 4 AGND1 Analog Ground Connection for the Output Driver. ...

  • Page 11

    ... BW Bandwidth. CRx A Control Register where placeholder for an alphabetic character (A–E). There are five read/ write control registers on the AD73311—desig- nated CRA through CRE. CRx:n A bit position, where placeholder for a nu- meric character (0–7), within a control register; where placeholder for an alphabetic charac- ter (A– ...

  • Page 12

    ... INTEREST 38 Figure 7 shows the various stages of filtering that are employed in a typical AD73311 application. In Figure 7a we see the trans- fer function of the external analog antialias filter. Even though single RC pole, its cutoff frequency is sufficiently far away from the initial sampling frequency (DMCLK/8) that it takes care of any signals that could be aliased by the sampling frequency ...

  • Page 13

    ... INTER d. Final Filter LPF (HPF) Transfer Function Decimation Filter The digital filter used in the AD73311 carries out two important functions. Firstly, it removes the out-of-band quantization noise, which is shaped by the analog modulator and secondly, it decimates the high frequency bit-stream to a lower rate 15-bit word ...

  • Page 14

    ... SPORT Overview The AD73311 SPORT is a flexible, full-duplex, synchronous serial port whose protocol has been designed to allow up to eight AD73311 devices to be connected, in cascade single DSP via a six-wire interface. It has a very flexible architecture that can be configured by programming two of the internal control registers ...

  • Page 15

    ... The control register bank consists of five read/write registers, each 8 bits wide. Table IX shows the control register map for the AD73311. The first two control registers, CRA and CRB, are reserved for control- ling the SPORT. They hold settings for parameters such as bit ...

  • Page 16

    ... If the address is not zero decremented and the control word is passed out of the device via the serial output. This 3-bit field is used to select one of the five control registers on the AD73311. This 8-bit field holds the data that written to or read from the selected register provided the address field is zero ...

  • Page 17

    ... ADC Power (0 = Power Down Power On) PUDAC DAC Power (0 = Power Down Power On) PUREF REF Power (0 = Power Down Power On) RU REFOUT Use (0 = Disable REFOUT Enable REFOUT) 5VEN Enable 5 V Operating Mode (0 = Disable 5 V Mode Enable 5 V Mode) AD73311 DATA/ ALB MM PGM ...

  • Page 18

    ... AD73311 7 CONTROL REGISTER D MUTE Bit CONTROL REGISTER E 0 Bit Table XIV. Control Register D Description OGS2 OGS1 OGS0 RMOD Name Description IGS0 Input Gain Select (Bit 0) IGS1 Input Gain Select (Bit 1) IGS2 ...

  • Page 19

    ... DMCLK/2048, until Control Register B is program- med after which the SDOFS pulses will revert to the DMCLK/256 rate. This is to allow slow controller devices to establish com- munication with the AD73311. During Program Mode, the data output by the device is random and should not be inter- preted as ADC data. ...

  • Page 20

    ... AD73311 SE SCLK SDOFS SDO SDIFS SDI DATA (CONTROL) WORD (DEVICE 1) SE SCLK SDOFS(2) SDO(2) SDOFS(1) SDIFS(2) SDO(1) SDI(2) SDIFS(1) SDI(1) DATA (CONTROL) WORD (DEVICE 2) SAMPLE WORD (DEVICE 1) SAMPLE WORD (DEVICE 2) SAMPLE WORD (DEVICE 1) DATA (CONTROL) WORD (DEVICE 2) SAMPLE WORD (DEVICE 1) DATA (CONTROL) WORD (DEVICE 1) ...

  • Page 21

    ... SDO RFS SDOFS Cascade Operation The AD73311 has been designed to support up to eight codecs in a cascade connected to a single serial port, see Figure 31. The SPORT interface protocol has been designed so that device addressing is built into the packet of information sent to the device. This allows the cascade to be formed with no extra hard- ware overhead for control signals or addressing ...

  • Page 22

    ... PERFORMANCE As the AD73311 is designed to provide high performance, low cost conversion important to understand the means by which this high performance can be achieved in a typical applica- tion. This section will, by means of spectral graphs, outline the typical performance of the device and highlight some of the ...

  • Page 23

    ... FREQUENCY – kHz Encoder Group Delay The AD73311 implementation offers a very low level of group delay, which is given by the following relationship: Group Delay (Decimator) = Order × ((M–1)/2) × Tdec where: Order is the order of the decimator (= 3 the decimation factor (= 32) and 3 Tdec is the decimation sample interval (= 1/2.048e6) => ...

  • Page 24

    ... The AD73311’s on-chip 38 dB preamplifier can be enabled when there is not enough gain in the input circuit; the preamplifier is configured by bits IGS0–2 of CRD. The total gain must be configured to ensure that a full-scale input signal produces a signal level at the input to the sigma-delta modulator of the ADC that does not exceed the maximum input range ...

  • Page 25

    ... AD73311 VOLTAGE REFERENCE Digital Interfacing The AD73311 is designed to easily interface to most common DSPs. The SCLK, SDO, SDOFS, SDI and SDIFS must be connected to the SCLK, DR, RFS, DT and TFS pins of the DSP respectively. The SE pin may be controlled from a parallel output pin or flag pin such as FL0–2 on the ADSP-21xx (or XF ...

  • Page 26

    ... Avoid running digital lines under the device for they will couple noise onto the die. The analog ground plane should be allowed to run under the AD73311 to avoid noise coupling. The power supply lines to the AD73311 should use as large a trace as pos- MCLK sible to provide low impedance paths and reduce the effects of SE glitches on the power supply lines ...

  • Page 27

    ... In systems where a common supply voltage is used to drive both the AVDD and DVDD of the AD73311 recommended that the system’s AVDD supply be used. This supply should have the recommended analog supply decoupling between the AVDD ...

  • Page 28

    ... AD73311 APPENDIX A Programming a Single AD73311 for Data Mode Operation This section describes a typical sequence in programming a single codec to operate in normal DATA mode. It details the control (program) words that are sent to the device to configure its internal registers and shows the typical output data received during both program and data modes ...

  • Page 29

    ... APPENDIX B Programming a Single AD73311 for Mixed Mode Operation This section describes a typical sequence in programming a single codec to operate in mixed mode. The device is connected in Nonframe Sync Loop-Back Mode (see Figure 14), which allows the DSP’s Tx Reg to determine how many words are sent to the device. In Step 1, the part has just been reset and on the first output event the codec presents an invalid output word The DSP’ ...

  • Page 30

    ... Configuring a Cascade of Two AD73311s to Operate in Data Mode This section describes a typical sequence of control words that would be sent to a cascade of two AD73311s to set them up for operation not intended definitive initialization sequence, but will show users the typical input/output events that occur in the programming and operation phases description panel refers to Figure 35 ...

  • Page 31

    ... DEVICE 1 DEVICE 2 ADC WORD 1 1010 1010 1010 1010 DEVICE 1 DEVICE 2 DAC WORD 2 0111 1111 1111 1111 AD73311 DSP RX REG DON'T CARE XXXX XXXX XXXX XXXX DSP RX REG ADC WORD 2 * 0000 0000 0000 0000 DSP RX REG ADC WORD 1 * ...

  • Page 32

    ... Configuring a Cascade of Two AD73311s to Operate in Mixed Mode This section describes a typical sequence of control words that would be sent to a cascade of two AD73311s to configure them for operation in mixed mode not intended definitive initialization sequence, but will show users the typical input/ ...

  • Page 33

    ... DEVICE 1 DEVICE 2 DON'T CARE XXXX XXXX XXXX XXXX DEVICE 1 DEVICE 2 ADC WORD 2 0100 0000 0000 0000 AD73311 DSP RX REG DON'T CARE XXXX XXXX XXXX XXXX DSP RX REG ADC WORD 2 * 0000 0000 0000 0000 DSP RX REG ADC WORD 1 * ...

  • Page 34

    ... DAC LOAD FROM DAC REGISTER process this information and generate a DAC word to be sent to the AD73311. Time t sending the DAC word to the AD73311. This sequence ends at time t where the DAC register will be updated from the 16 bits 4 in the AD73311’s serial register. However, the DAC will not be updated from the DAC register until time t acceptable in certain applications ...

  • Page 35

    ... SPORT Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SPORT Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Master Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial Clock Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 15 DAC Advance Register . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Page Topic OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Resetting the AD73311 . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Control Register Tables . . . . . . . . . . . . . . . . . . . . . . . 17, 18 Program (Control) Mode . . . . . . . . . . . . . . . . . . . . . . . . . 19 Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Mixed Program/Data Mode . . . . . . . . . . . . . . . . . . . . . . . 19 Analog Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Digital Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Interface Signal Timing ...

  • Page 36

    ... AD73311 20-Lead Small Outline IC (R-20) 0.5118 (13.00) 0.4961 (12.60 PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0500 0.0192 (0.49) 0.0118 (0.30) SEATING 0.0125 (0.32) (1.27) 0.0040 (0.10) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Shrink Small Outline IC 0.295 (7.50) 0.271 (6.90 0.0291 (0.74) 45 0.078 (1.98) PIN 1 0.0098 (0.25) 0.068 (1.73) 0.0500 (1.27 0.0157 (0.40) ...