ad73311 Analog Devices, Inc., ad73311 Datasheet - Page 21

• Manufacturer Part Number: ad73311
• Description: Low Cost, Low Power Cmos General Purpose Analog Front End
• Manufacturer: Analog Devices, Inc.

INTERFACING
The AD73311 can be interfaced to most modern DSP engines
using conventional serial port connections and an extra enable
control line. Both serial input and output data use an accompa-
nying frame synchronization signal which is active high one
clock cycle before the start of the 16-bit word or during the last
bit of the previous word if transmission is continuous. The serial
clock (SCLK) is an output from the codec and is used to define
the serial transfer rate to the DSP’s Tx and Rx ports. Two primary
configurations can be used: the first is shown in Figure 12 where
the DSP’s Tx data, Tx frame sync, Rx data and Rx frame sync
are connected to the codec’s SDI, SDIFS, SDO and SDOFS
respectively. This configuration, referred to as indirectly coupled
or nonframe sync loop-back, has the effect of decoupling the
transmission of input data from the receipt of output data. The
delay between receipt of codec output data and transmission of
input data for the codec is determined by the DSP’s software
latency. When programming the DSP serial port for this con-
figuration, it is necessary to set the Rx FS as an input and the
Tx FS as an output generated by the DSP. This configuration is
most useful when operating in mixed mode, as the DSP has the
ability to decide how many words (either DAC or control) can be
sent to the codec(s). This means that full control can be imple-
mented over the device configuration as well as updating the
DAC in a given sample interval. The second configuration
(shown in Figure 13) has the DSP’s Tx data and Rx data con-
nected to the codec’s SDI and SDO, respectively while the
DSP’s Tx and Rx frame syncs are connected to the codec’s
SDIFS and SDOFS. In this configuration, referred to as directly
coupled or frame sync loop-back, the frame sync signals are
connected together and the input data to the codec is forced to
be synchronous with the output data from the codec. The DSP
must be programmed so that both the Tx FS and Rx FS are
inputs as the codec SDOFS will be input to both. This configu-
ration guarantees that input and output events occur simulta-
neously and is the simplest configuration for operation in
normal Data Mode. Note that when programming the DSP in
this configuration it is advisable to preload the Tx register with
the first control word to be sent before the codec is taken out of
reset. This ensures that this word will be transmitted to coincide
with the first output word from the device(s).
ADSP-21xx
DSP
DT
DR
RFS
TFS
SCLK
SDOFS
SDIFS
SCLK
SDO
SDI
AD73311
CODEC
Cascade Operation
The AD73311 has been designed to support up to eight codecs
in a cascade connected to a single serial port, see Figure 31.
The SPORT interface protocol has been designed so that device
addressing is built into the packet of information sent to the
device. This allows the cascade to be formed with no extra hard-
ware overhead for control signals or addressing. A cascade can
be formed in either of the two modes previously discussed.
There may be some restrictions in cascade operation due to the
number of devices configured in the cascade and the serial clock
rate chosen. Table XVI details the requirements for SCLK rate
for cascade lengths from 1 to 8 devices. This assumes a directly
coupled frame sync arrangement as shown in Figure 13.
SCLK
DMCLK
DMCLK/2
DMCLK/4
DMCLK/8
When using the indirectly coupled frame sync configuration in
cascaded operation it is necessary to be aware of the restrictions
in sending data to all devices in the cascade. Effectively the time
allowed is given by the sampling interval (256/DMCLK) which
is 15.625 µs for a sample rate of 64 kHz. In this interval, the
DSP must transfer N × 16 bits of information where N is the
number of devices in the cascade. Each bit will take 1/SCLK
and, allowing for any latency between the receipt of the Rx
interrupt and the transmission of the Tx data, the relationship
for successful operation is given by:
The interrupt latency will include the time between the ADC
sampling event and the Rx interrupt being generated in the
DSP—this should be 16 SCLK cycles.
In Cascade Mode, each device must know the number of
devices in the cascade because the Data and Mixed modes use a
method of counting input frame sync pulses to decide when they
should update the DAC register from the serial input register.
ADSP-21xx
256/DMCLK > ((N/SCLK) + T
DSP
Table XVI. Cascade Options
Number of Devices in Cascade
1




TFS
DT
SCLK
DR
RFS
2




3



X
SDOFS
4



X
SDIFS
SCLK
SDO
INTERRUPT LATENCY
SDI
5


X
X
AD73311
AD73311
CODEC
6


X
X
7


X
X
)
8


X
X