ad73460 Analog Devices, Inc., ad73460 Datasheet

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... Power Dissipation with 400 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode GENERAL DESCRIPTION The AD73460 is a six-input channel analog front end processor for general-purpose applications including industrial power meter- ing or multichannel analog inputs. It features six 16-bit A/D conversion channels, each of which provides 72 dB signal-to-noise ratio over a dc-to-2 kHz signal bandwidth ...

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... AD73460 TABLE OF CONTENTS Topic FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 6 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PBGA BALL CONFIGURATION . . . . . . . . . . . . . . . . . . . . 7 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 8 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 10 ANALOG FRONT END . . . . . . . . . . . . . . . . . . . . . . . . . . 10 FUNCTIONAL DESCRIPTION–AFE . . . . . . . . . . . . . . . 11 Encoder Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Signal Conditioner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 11 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Analog Sigma-Delta Modulator . . . . . . . . . . . . . . . . . . . . 12 Decimation Filter ...

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... AD73460 = 16.384 MHz 8.192 MHz, MCLK SCLK 1 Test Conditions/Comments 0.1 µF Capacitor Required from REFCAP to AGND2 Unloaded Measured Differentially Measured Differentially 1.0 kHz kHz kHz kHz kHz ...

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... REFOUT Only On 4.5 All Sections On 26.5 All Sections Off 1.5 All Sections Off 0.1 The above values are in mA. MCLK = 16.384 MHz; SCLK = 16.384 MHz. (AVDD = 3 3.6 V; DVDD = 3 3.6 V; DGND = AGND = 16.384 MHz, f MCLK SAMP AD73460B Min Typ Max Unit V – 0 0.8 V µA ...

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... Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7 BR. 9 Idle refers to AD73460 state of operation during execution of IDLE instruction. Deasserted pins are driven to either and 3 V. For typical figures for supply currents, refer to Power Dissipation section. IN ...

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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD73460 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. (AVDD = 3.6 V ...

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... –7– AD73460 Ball PBGA Ball Name Number Name D22 N7 D13 EBR D21 P1 D20 P2 D0/IAD13 ELOUT P3 DVDD ELIN P4 DGND EINT ARESET P5 D19 P6 SCLK2 D18 P7 MCLK D17 ...

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... SDIFS is sampled on the negative edge of SCLK2 and is ignored when SE is low. SDI Serial Data Input of the AD73460. Both data and control information may be input on this pin and are clocked on the negative edge of SCLK2. SDI is ignored when SE is low. SE SPORT Enable ...

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... Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag. 3 SPORT configuration determined by the DSP System Control Register. Software configurable. REV PIN FUNCTION DESCRIPTIONS (continued) 2 Programmable I/O Pin –9– AD73460 ...

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... All channels share a common internal reference whose nominal value is 1.25 V. Figure 2 shows a block diagram of the AFE section of the AD73460. It shows six input channels along with a common reference. Communication to all channels is handled by the SPORT2 block, which interfaces to either SPORT0 or SPORT1 of the DSP section. – ...

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... DMCLK/8 rate. This bit stream, representing the analog input signal, is input to the antialiasing decimation filter. The decimation filter reduces the sample rate and increases the resolution. –11– AD73460 AD73460 SDI SDIFS SCLK2 ARESET SERIAL I/O ...

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... Figure 3. Sigma-Delta Noise Reduction Figure 4 shows the various stages of filtering that are employed in a typical AD73460 application. In Figure 4a we see the trans- fer function of the external analog antialias filter. Even though single RC pole, its cutoff frequency is sufficiently far away from the initial sampling frequency (DMCLK/8) that it takes care of any signals that could be aliased by the sampling frequency ...

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... ADC CODE SINGLE-ENDED Figure 5. ADC Transfer Function Voltage Reference The AD73460 contains an internal band gap reference that provides a low noise, temperature-compensated reference to the ADCs. The reference has a nominal value of 1.25 V and is available on the REFCAP pin. A buffered version of the reference is available on the REFOUT pin and can be used to bias external analog circuitry if required ...

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... AD73460 words to the AFE. In certain configurations, data can be written to the device to coincide with the output sample being shifted out of the serial register—see section on interfacing devices. The serial clock rate (CRB:2–3) defines how many 16-bit words can be written to a device before the next output sample event will happen ...

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... R/W DEVICE ADDRESS C/D Control Frame Bit 15 CONTROL/DATA Bit 14 READ/WRITE Bits 13–11 DEVICE ADDRESS Bits 10–8 REGISTER ADDRESS This 3-bit field is used to select one of the eight control registers on the AD73460. Bits 7–0 REGISTER DATA CONTROL REGISTER A 7 RESET Bit REV ...

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... AD73460 CONTROL REGISTER B 7 CEE Bit CONTROL REGISTER C RES Bit CONTROL REGISTER D PUI2 Bit Table IX. Control Register B Description MCD2 MCD1 MCD0 SCD1 Name Description DR0 Decimation Rate (Bit 0) ...

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... Channel 1 Select CH2 Channel 2 Select CH3 Channel 3 Select CH4 Channel 4 Select CH5 Channel 5 Select CH6 Channel 6 Select RMOD Reset Analog Modulator SEEN Enable Single-Ended Input Mode –17– AD73460 PUI3 I3GS2 I3GS1 I3GS0 PUI5 I5GS2 I5GS1 I5GS0 ...

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... AD73460 CONTROL REGISTER H 7 INV Bit OPERATION Resetting the AFE The ARESET pin resets all the control registers. All the AFE registers are reset to zero, indicating that the default SCLK2 rate (DMCLK/8) and sample rate (DMCLK/2048) are at a mini- mum ...

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... Tx and Rx ports. Two primary configurations can be used: the first is shown in Figure 8 where the DSP’s Tx data, Tx frame sync, Rx data and Rx frame sync are connected to the AD73460’s SDI, SDIFS, SDO, and SDOFS, respectively. This configuration, referred to as indirectly coupled or nonframe sync loop-back, has the effect of decoupling the transmission of input data from the receipt of output data ...

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... The AD73460 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. Figure overall block diagram of the AD73460. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data directly and have provi- sions to support multiprecision computations ...

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... The AD73460 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the AD73460 SPORTs. For additional information on Serial Ports, refer to the ADSP- 2100 Family User’s Manual, Third Edition. ...

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... AD73460 Full Memory Mode Pins (Mode Pin # of Input/ Name(s) Pins Output Function A13 Address Output Pins for Program, Data, Byte, and I/O Spaces D23:0 24 I/O Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used as Byte Memory addresses) Host Mode Pins (Mode ...

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... Power-down acknowledge pin indicates when the processor has entered power-down. Idle When the AD73460 is in the Idle Mode, the processor waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs serviced; execution then con- tinues with the instruction following the IDLE instruction. In Idle Mode IDMA, BDMA, and autobuffer cycle steals still occur ...

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... The signal is connected to the processor’s CLKIN input. When an external clock is used, the XTAL input must be left unconnected. The AD73460 uses an input clock with a frequency equal to half the instruction rate; a 26.00 MHz input clock yields processor cycle (which is equivalent to 52 MHz). Normally, instructions are executed in a single processor cycle ...

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... Considered as standard operating settings. Using these configurations allows for easier design and better memory management. RESET The RESET signal initiates a master reset of the AD73460. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabi- lize ...

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... Data Memory (Full Memory Mode 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. The AD73460-80 has 16K words on Data Memory RAM on-chip (the AD73460-40 has 8K words on Data Memory RAM on-chip), consisting of 16,352 user-accessible locations in the case of the AD73460-80 (8,160 user-accessible locations in the case of the AD73460-40) and 32 memory-mapped registers ...

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... Mode) BCR The IDMA Port provides an efficient means of communication 0 = RUN DURING BDMA 1 = HALT DURING BDMA between a host system and the AD73460. The port is used to access the on-chip program memory and data memory of the –27– AD73460 Table XXII. Data Formats Internal ...

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... DMA operation. Asserting the IDMA port select (IS) and address latch enable (IAL) directs the AD73460 to write the address onto the IAD0–14 bus into the IDMA Control Register. If IAD[15] is set to 0, IDMA latches the address. The IDMAA register, shown below, is memory mapped at address DM (0x3FE0) ...

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... The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when the AD73460 is ready to execute an instruction, but is stopped because the external bus is already granted to another device. The other device can release the bus by deasserting the bus request ...

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... AD73460 The EZ-ICE uses the EE (emulator enable) signal to take control of the AD73460 in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your system. ...

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... Figure 20. DSP to AD73460 AFE Connection CASCADE OPERATION Where it is required to configure an extra analog input channel to the existing six channels on the AD73460 possible to cascade six more channels (using external AD73360 AFEs) by using the scheme described in Figure 22 necessary how- ever to ensure that the timing of the SE and ARESET signals is synchronized at each device in the cascade ...

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... High speed serial clocks will read the data from the AD73460 in a shorter time, giving more time for processing at the expense of injecting some digital noise into the circuit. Digital noise can also be reduced by connecting resistors (typ < ...