ad73422 Analog Devices, Inc., ad73422 Datasheet

ad73422

Manufacturer Part Number

ad73422

Description

Dual Low Power Cmos Analog Front End With Dsp Microcomputer

Manufacturer

Analog Devices, Inc.

Datasheet

1.AD73422.pdf (36 pages)

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GENERAL DESCRIPTION

The AD73422 is a single device incorporating a dual analog

front end and a microcomputer optimized for digital signal

processing (DSP) and other high speed numeric processing

applications.

The AD73422’s analog front end (AFE) section features a dual

front-end converter for general purpose applications including

speech and telephony. The AFE section features two 16-bit A/D

conversion channels and two 16-bit D/A conversion channels.

Each channel provides 77 dB signal-to-noise ratio over a

voiceband signal bandwidth. It also features an input-to-output

gain network in both the analog and digital domains. This is

featured on both codecs and can be used for impedance match-

ing or scaling when interfacing to Subscriber Line Interface

Circuits (SLICs).

The AD73422 is particularly suitable for a variety of applica-

tions in the speech and telephony area including low bit rate,

high quality compression, speech enhancement, recognition

and synthesis. The low group delay characteristic of the AFE

makes it suitable for single or multichannel active control

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

REV. 0

FEATURES

AFE PERFORMANCE

Two 16-Bit A/D Converters

Two 16-Bit D/A Converters

Programmable Input/Output Sample Rates

78 dB ADC SNR

77 dB DAC SNR

64 kS/s Maximum Sample Rate

–90 dB Crosstalk

Low Group Delay (25 s Typ per ADC Channel,

Programmable Input/Output Gain

On-Chip Reference

DSP PERFORMANCE

19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS

Single-Cycle Instruction Execution

Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby

Low Power Dissipation in Idle Mode

50 s Typ per DAC Channel)

Sustained Performance

Every Instruction Cycle

Power Dissipation with 400 Cycle Recovery from

Power-Down Condition

Analog Front End with DSP Microcomputer

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

applications. The A/D and D/A conversion channels feature

programmable input/output gains with ranges 38 dB and 21 dB

respectively. An on-chip reference voltage is included to allow

single supply operation.

The sampling rate of the AFE is programmable with four sepa-

rate settings offering 64, 32, 16 and 8 kHz sampling rates (from

a master clock of 16.384 MHz), while the serial port (SPORT2)

allows easy expansion of the number of I/O channels by cascad-

ing extra AFEs external to the AD73422.

The AD73422’s DSP engine combines the ADSP-2100 family

base architecture (three computational units, data address gen-

erators and a program sequencer) with two serial ports, a 16-bit

internal DMA port, a byte DMA port, a programmable timer,

Flag I/O, extensive interrupt capabilities and on-chip program

and data memory.

The AD73422-80 integrates 80K bytes of on-chip memory

configured as 16K words (24-bit) of program RAM, and 16K

words (16-bit) of data RAM. The AD73422-40 integrates 40K

bytes of on-chip memory configured as 8K words (24-bit) of

program RAM, and 8K words (16-bit) of data RAM. Power-

down circuitry is also provided to meet the low power needs of

battery operated portable equipment. The AD73422 is available

in a 119-ball PBGA package.

GENERATORS

DAG 1

ADDRESS

ALU

DATA

ARITHMETIC UNITS

ADSP-2100 BASE

ARCHITECTURE

DAG 2

MAC

SEQUENCER

FUNCTIONAL BLOCK DIAGRAM

PROGRAM

SHIFTER

DATA MEMORY DATA

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

REF

Dual Low Power CMOS

ADC1

World Wide Web Site: http://www.analog.com

(OPTIONAL

SPORT 0

16K PM

ANALOG FRONT END

POWER-DOWN

8K)

SERIAL PORTS

DAC1

CONTROL

MEMORY

SERIAL PORT

SECTION

SPORT 2

(OPTIONAL

SPORT 1

16K DM

8K)

ADC2

TIMER

PROGRAMMABLE

DAC2

AD73422

FLAGS

AND

I/O

FULL MEMORY

CONTROLLER

HOST MODE

EXTERNAL

BYTE DMA

ADDRESS

INTERNAL

MODE

DATA

PORT

BUS

DMA

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