ad7008 Analog Devices, Inc., ad7008 Datasheet
ad7008
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ad7008 Summary of contents
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... Frequency, Phase or Amplitude Modulators DDS Tuning Digital Modulation PRODUCT DESCRIPTION The AD7008 direct digital synthesis chip is a numerically con- trolled oscillator employing a 32-bit phase accumulator, sine and cosine look-up tables and a 10-bit D/A converter integrated on a single CMOS chip. Modulation capabilities are provided for ...
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... 4.75 5.25 4. 1.5/MHz 80 110 10 = 2.11 MHz. OUT . + I shown above –2– 390 , for MIN MAX SET LOAD AD7008JP50 Test Conditions/ Typ Max Units Comments Bits 50 MSPS Volts +1 LSB 1 LSB 50 MSPS CLK MHz OUT CLK ...
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... VALID D0–D15 t 6 SCLK t 9 SDATA –3– AD7008 Test Conditions/Comments CLOCK Period CLOCK High Duration CLOCK Low Duration CLOCK to Control Setup Time CLOCK to Control Hold Time LOAD Period 1 LOAD High Duration LOAD High to TC0–TC3 Setup Time LOAD High to TC0–TC3 Hold Time ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7008 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Serial Data, digital input. Serial data is clocked on the rising edge of SCLK, Most Significant Bit (MSB) first. SLEEP Low power sleep control, active high digital input. SLEEP puts the AD7008 into a low power sleep mode. Inter- nal clocks are disabled, while also turning off the DAC current sources. A SLEEP bit is also provided in the COMMAND REG to put the AD7008 into a low power sleep mode ...
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... AD7008 14 PIPELINE DELAYS ACCUMULATOR 32 AD7008 REGISTER AND 12 CONTROL LOGIC 20 ACCUM RESET SLEEP AM ENABLE Figure 7. AD7008 CMOS DDS Modulator (See Table I) SLEEP (37) SCLK (41 SDATA (42) 32-BIT SERIAL ASSEMBLY REGISTER 32-BIT PARALLEL ASSEMBLY REGISTER 23 15:0 23:8 1 D0-D15 15:8 7:0 (19-26, 8-15) 7 (16 (27) D FLIP-FLOPS ARE MASTER SLAVE, LATCHING DATA ON CLK RISING EDGE ...
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... Serial 1 1 Serial Table III. AD7008 Control Registers Reset State Description All Zeros Command Register. This is written to using the parallel assembly register. Frequency Register 0. This defines the output frequency, when FSELECT = fraction of the CLOCK frequency. Frequency Register 1. This defines the output frequency, when FSELECT = fraction of the CLOCK frequency ...
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... SINE/CO- SINE look-up tables, frequency, phase and IQ modulators, and a digital-to-analog converter on a single integrated circuit. The internal circuitry of the AD7008 consists of four main sec- tions. These are: Numerically Controlled Oscillator (NCO) + Phase Modulator SINE and COSINE Look-Up Tables ...
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... Figure 10. Accelerated Data Load Sequence APPLICATIONS Serial Configuration Data is written to the AD7008 in serial mode using the two sig- nal lines SDATA and SCLK. Data is accumulated in the serial assembly register with the most significant bit loaded first. The data bits are loaded on the rising edge of the serial clock. Once data is loaded in the serial assembly register, it must be trans- ferred to the appropriate register on chip ...
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... TEST dm(dds_para)=r4 0x80000000; {Transfer data from the dm(dds_cont)=r4; Local Oscillator The AD7008 is well suited for applications such as local oscilla- tors used in super-heterodyne receivers. Although the AD7008 can be used in a variety of receiver designs, one simple local os- 10 VMID BANDPASS FILTER ...
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... FREQ 1 REG Figure 14. FSK Modulator The AD7008 has three registers that can be used for modula- tion. Besides the example of frequency modulation shown above, the frequency registers can be updated dynamically as can the phase register and the IQMOD register. These can be modulated at rates up to 16.5 MHz. The example shown below along with code fragment shows how to implement the AD7008 in an amplitude modulation scheme ...
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... AD7008–Typical Performance Characteristics +5V V COMP REF 6 5 115 TO DAC TYP V REF AD7008 4 R SET Figure 17. Equivalent Reference Circuit REF 4.3 dBm OFFSET 3 330 000 dB/DIV RANGE 5.0 dBm START 0 Hz RBW 3 kHz VBW 10 kHz Figure 18 MHz, f CLK OUT REF 4.3 dBm OFFSET 4 500 000 ...
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... RANGE 5.0 dBm START 0 Hz RBW 3 kHz VBW 10 kHz Figure 25 MHz, f CLK OUT REV. B Typical Performance Characteristics–AD7008 REF 4.3 dBm OFFSET 1 680 000 dB/DIV –52.8 dB CENTER 16 000 000.0 Hz STOP 10 000 000 2.4 SEC Figure 26 6.1 MHz OFFSET 500 000.0 Hz – ...
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... AD7008–Typical Performance Characteristics REF 5.0 dBm OFFSET 4 500 000 dB/DIV RANGE 5.0 dBm START 0 Hz RBW 3 kHz VBW 10 kHz Figure 29 MHz, f CLK OUT REF 5.0 dBm OFFSET 11 100 000 dB/DIV RANGE 5.0 dBm START 0 Hz RBW 3 kHz VBW 10 kHz Figure 30 MHz, f ...
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... CMOS clock input HIGH CMOS clock input LOW USING THE AD7008/PCB DDS EVALUATION BOARD The AD7008/PCB evaluation kit is a test system designed to simplify the evaluation of the AD7008 50 MHz Direct Digital Synthesizer. Provisions to control the AD7008 from the printer port of an IBM-compatible PC are included, along with the REV ...
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... V and ground power connection. LK1 External sleep command input. A 3.5" floppy disk containing software to control the AD7008 is provided with the AD7008/PCB. This software was developed using C. The C source code is provided in a file named A:\AD7008.C, which the user may view, run, or modify. ...