mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet

mt48lc1m16a1

Manufacturer Part Number

mt48lc1m16a1

Description

Synchronous Dram

Manufacturer

Micron Semiconductor Products

Datasheet

1.MT48LC1M16A1.pdf (51 pages)

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SYNCHRONOUS

DRAM

FEATURES

• PC100 functionality

• Fully synchronous; all signals registered on

• Internal pipelined operation; column address can

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8 or full page

• Auto Precharge Mode, includes CONCURRENT

• Self Refresh and Adaptable Auto Refresh Modes

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

• Supports CAS latency of 1, 2 and 3

• Industrial temperature range: -40°C to +85°C

OPTIONS

• Configuration

• Plastic Package - OCPL*

• Timing (Cycle Time)

• Refresh

• Operating Temperature

16Mb: x16 IT SDRAM

16MSDRAMx16IT.p65 – Rev. 5/99

positive edge of system clock

be changed every clock cycle

1 Meg x 16 - 512K x 16 x 2 banks architecture with

11 row, 8 column addresses per bank

AUTO PRECHARGE

- 32ms, 2,048-cycle refresh or

- 64ms, 2,048-cycle refresh or

- 64ms, 4,096-cycle refresh

1 Meg x 16 (512K x 16 x 2 banks)

50-pin TSOP (400 mil)

6ns (166 MHz)

7ns (143 MHz)

8ns (125 MHz)

2K or 4K with Self Refresh Mode at 64ms

-40°C to +85°C

MT48LC1M16A1TG-7SIT

Part Number Example:

MARKING

1M16A1

-8A

T G

-6

-7

MT48LC1M16A1 SIT - 512K x 16 x 2 banks

INDUSTRIAL TEMPERATURE

For the latest data sheet, please refer to the Micron Web site:

www.micronsemi.com/datasheets/sdramds.html

KEY TIMING PARAMETERS

*Off-center parting line

**CL = CAS (READ) latency

16MB (X16) SDRAM PART NUMBER

Note: The # symbol indicates signal is active LOW.

Configuration

Refresh Count

Row Addressing

Bank Addressing

Column Addressing

PART NUMBER

MT48LC1M16A1TG SIT

SPEED

-8A

-6

-7

PIN ASSIGNMENT (Top View)

DQML

CAS#

RAS#

Micron Technology, Inc., reserves the right to change products or specifications without notice.

VssQ

WE#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

A10

CS#

166 MHz

143 MHz

125 MHz

CLOCK

50-Pin TSOP

ACCESS TIME

CL = 3**

5.5ns

ARCHITECTURE

1 Meg x 16

6ns

512K x 16 x 2 banks

1 Meg x 16

2K (A0-A10)

256 (A0-A7)

2K or 4K

2 (BA)

16Mb: x16

IT SDRAM

SETUP

2ns

Vss

DQ15

DQ14

VssQ

DQ13

DQ12

DQ11

DQ10

VssQ

DQ9

DQ8

DQMH

CLK

CKE

Vss

HOLD

1ns

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