mt4lc4m4e9tg Micron Semiconductor Products, mt4lc4m4e9tg Datasheet

mt4lc4m4e9tg

Manufacturer Part Number

mt4lc4m4e9tg

Description

4 Meg X 4 Edo Dram

Manufacturer

Micron Semiconductor Products

Datasheet

1.MT4LC4M4E9TG.pdf (23 pages)

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DRAM

FEATURES

• Industry-standard x4 pinout, timing, functions and

• State-of-the-art, high-performance, low-power CMOS

• Single power supply (+3.3V 0.3V or +5V 10%)

• All inputs, outputs and clocks are TTL-compatible

• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-

• Optional Self Refresh (S) for low-power data retention

• 11 row, 11 column addresses (2K refresh) or

• Extended Data-Out (EDO) PAGE MODE access cycle

• 5V-tolerant inputs and I/Os on 3.3V devices

OPTIONS

• Voltages

• Refresh Addressing

• Packages

• Timing

• Refresh Rates

• Part Number Example: MT4LC4M4E8DJ-6

KEY TIMING PARAMETERS

4 Meg x 4 EDO DRAM

D47.pm5 – Rev. 3/97

SPEED

packages

silicon-gate process

BEFORE-RAS# (CBR)

12 row, 10 column addresses (4K refresh)

3.3V

2,048 (i.e. 2K) Rows

4,096 (i.e. 4K) Rows

Plastic SOJ (300 mil)

Plastic TSOP (300 mil)

50ns access

60ns access

Standard Refresh

Self Refresh (128ms period)

Note: The 4 Meg x 4 EDO DRAM base number differentiates the offerings in

two places - MT4LC4M4E8. The third field distinguishes the low voltage

offering: LC designates V

distinguishes various options: E8 designates a 2K refresh and E9 designates a

4K refresh for EDO DRAMs.

-5

-6

104ns

84ns

TECHNOLOGY, INC.

50ns

60ns

RAC

= 3.3V and C designates V

20ns

25ns

30ns

MARKING

= 5V. The fifth field

13ns

15ns

CAC

None

-5

-6

10ns

8ns

CAS

MT4LC4M4E8, MT4C4M4E8

MT4LC4M4E9, MT4C4M4E9

GENERAL DESCRIPTION

memory containing 16,777,216 bits organized in a x4 con-

figuration. RAS# is used to latch the row address (first 11

bits for 2K and first 12 bits for 4K). Once the page has been

opened by RAS#, CAS# is used to latch the column address

4 MEG x 4 EDO DRAM PART NUMBERS

* NC on 2K refresh and A11 on 4K refresh options.

Note: The “#” symbol indicates signal is active LOW.

PART NUMBER

MT4LC4M4E8DJ

MT4LC4M4E8DJS

MT4LC4M4E8TG

MT4LC4M4E8TGS

MT4LC4M4E9DJ

MT4LC4M4E9DJS

MT4LC4M4E9TG

MT4LC4M4E9TGS

MT4C4M4E8DJ

MT4C4M4E8DJS

MT4C4M4E8TG

MT4C4M4E8TGS

MT4C4M4E9DJ

MT4C4M4E9DJS

MT4C4M4E9TG

MT4C4M4E9TGS

*NC/A11

The 4 Meg x 4 DRAM is a randomly accessed, solid-state

RAS#

WE#

DQ1

DQ2

A10

24/26-Pin SOJ

PIN ASSIGNMENT (Top View)

(DA-2)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

3.3V

Vcc

DQ4

DQ3

CAS#

OE#

REFRESH

*NC/A11

RAS#

WE#

DQ1

DQ2

A10

24/26-Pin TSOP

PACKAGE

EDO DRAM

(DB-2)

TSOP

SOJ

4 MEG x 4

1997, Micron Technology, Inc.

Standard

REFRESH

Self

DQ4

DQ3

CAS#

OE#

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