mt4lc4m4e8tg-6-s Micron Semiconductor Products, mt4lc4m4e8tg-6-s Datasheet

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mt4lc4m4e8tg-6-s

Manufacturer Part Number
mt4lc4m4e8tg-6-s
Description
16mb Edo Mt4lc4m4e8dj-5
Manufacturer
Micron Semiconductor Products
Datasheet
DRAM
FEATURES
• Industry-standard x4 pinout, timing, functions and
• High-performance, low-power CMOS silicon-gate
• Single +3.3V ±0.3V power supply
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-
• Optional self refresh (S) for low-power data retention
• 11 row, 11 column addresses (2K refresh) or
• Extended Data-Out (EDO) PAGE MODE access
OPTIONS
• Refresh Addressing
• Packages
• Timing
• Refresh Rates
NOTE:
*Contact factory for availability
KEY TIMING PARAMETERS
GENERAL DESCRIPTION
memory containing 16,777,216 bits organized in a x4 con-
figuration. RAS# is used to latch the row address (first 11
bits for 2K and first 12 bits for 4K). Once the page has been
opened by RAS#, CAS# is used to latch the column address
4 Meg x 4 EDO DRAM
D47.p65 – Rev. 6/98
SPEED
The 4 Meg x 4 DRAM is a randomly accessed, solid-state
packages
process
BEFORE-RAS# (CBR)
12 row, 10 column addresses (4K refresh)
2,048 (2K) rows
4,096 (4K) rows
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
50ns access
60ns access
Standard Refresh
Self Refresh (128ms period)
-5
-6
1. The 4 Meg x 4 EDO DRAM base number differentiates the
2. The “#” symbol indicates signal is active LOW.
offerings in one place - MT4LC4M4E8. The fifth field
distinguishes various options: E8 designates a 2K refresh and E9
designates a 4K refresh for EDO DRAMs.
104ns
84ns
t
RC
50ns
60ns
t
RAC
20ns
25ns
t
PC
25ns
30ns
t
AA
MARKING
13ns
15ns
t
CAC
None
TG
E8
E9
DJ
-5
-6
S*
10ns
t
8ns
CAS
1
MT4LC4M4E8, MT4LC4M4E9
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/mti/msp/html/datasheet.html
4 MEG x 4 EDO DRAM PART NUMBERS
x = speed
(the latter 11 bits for 2K and the latter 10 bits for 4K; address
pins A10 and A11 are “Don’t Care”). READ and WRITE
cycles are selected with the WE# input.
LOW on WE# dictates write mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE# or CAS#,
whichever occurs last. An EARLY WRITE occurs when
WE# is taken LOW prior to CAS# falling. A LATE WRITE or
READ-MODIFY-WRITE occurs when WE# falls after CAS#
is taken LOW. During EARLY WRITE cycles, the data
outputs (Q) will remain High-Z regardless of the state of
OE#. During LATE WRITE or READ-MODIFY-WRITE
** NC on 2K refresh and A11 on 4K refresh options.
**NC/A11
PART NUMBER
MT4LC4M4E8DJ-x
MT4LC4M4E8DJ-x S
MT4LC4M4E8TG-x
MT4LC4M4E8TG-x S
MT4LC4M4E9DJ-x
MT4LC4M4E9DJ-x S
MT4LC4M4E9TG-x
MT4LC4M4E9TG-x S
A logic HIGH on WE# dictates read mode, while a logic
RAS#
WE#
DQ0
DQ1
V
A10
V
24/26-Pin SOJ
A0
A1
A2
A3
DD
DD
PIN ASSIGNMENT (Top View)
1
2
3
4
5
6
8
9
10
11
12
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
26
25
24
23
22
21
19
18
17
16
15
14
ADDRESSING
REFRESH
V
DQ3
DQ2
CAS #
OE #
A9
A8
A7
A6
A5
A4
V
SS
SS
2K
2K
2K
2K
4K
4K
4K
4K
**NC/A11
RAS#
WE#
DQ0
DQ1
24/26-Pin TSOP
V
A10
V
A0
A1
A2
A3
DD
DD
PACKAGE
EDO DRAM
TSOP
TSOP
TSOP
TSOP
SOJ
SOJ
SOJ
SOJ
1
2
3
4
5
6
8
9
10
11
12
13
4 MEG x 4
1998, Micron Technology, Inc.
Standard
Standard
Standard
Standard
REFRESH
26
25
24
23
22
21
19
18
17
16
15
14
Self
Self
Self
Self
V
DQ3
DQ2
CAS#
OE#
A9
A8
A7
A6
A5
A4
V
SS
SS

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mt4lc4m4e8tg-6-s Summary of contents

Page 1

... MEG x 4 EDO DRAM PART NUMBERS DJ TG PART NUMBER -5 MT4LC4M4E8DJ-x -6 MT4LC4M4E8DJ-x S MT4LC4M4E8TG-x None MT4LC4M4E8TG MT4LC4M4E9DJ-x MT4LC4M4E9DJ-x S MT4LC4M4E9TG-x MT4LC4M4E9TG speed (the latter 11 bits for 2K and the latter 10 bits for 4K; address pins A10 and A11 are “Don’t Care”). READ and WRITE t ...

Page 2

GENERAL DESCRIPTION (continued) cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data LATE WRITE or READ- MODIFY-WRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data outputs ...

Page 3

EDO PAGE MODE (continued) tively, pulsing WE# to the idle banks during CAS# HIGH time will also High-Z the outputs. Independent of OE# control, the outputs will disable after enced from the rising edge of RAS# or CAS#, whichever occurs ...

Page 4

FUNCTIONAL BLOCK DIAGRAM - 2K REFRESH WE# CAS# NO. 2 CLOCK GENERATOR COLUMN- ADDRESS A0 11 BUFFER(11 REFRESH A3 CONTROLLER REFRESH A7 COUNTER A10 ROW- ADDRESS 11 BUFFERS (11) NO. 1 CLOCK ...

Page 5

ABSOLUTE MAXIMUM RATINGS* Voltage on V Pin Relative Voltage on NC, Inputs or I/O Pins Relative to V ................................................ -1V to +4.6V SS Operating Temperature, T (ambient) .......... 0°C to +70°C A Storage Temperature (plastic) ................... ...

Page 6

Icc OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes +3.3V ± 0.3V) DD PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS STANDBY CURRENT: CMOS (non-“S” version only) (RAS# = CAS# = other ...

Page 7

CAPACITANCE PARAMETER Input Capacitance: Address pins Input Capacitance: RAS#, CAS#, WE#, OE# Input/Output Capacitance ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12 +3.3V ± 0.3V CHARACTERISTICS PARAMETER Access time from column address Column-address ...

Page 8

AC ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12 +3.3V ± 0.3V CHARACTERISTICS PARAMETER OE# setup prior to RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time ...

Page 9

NOTES 1. All voltages referenced The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0˚C ≤ T ≤ 70˚C) is ensured initial ...

Page 10

V IH RAS CRP V CAS ASR V IH ROW ADDR WE OE TIMING PARAMETERS -5 SYMBOL MIN ...

Page 11

V IH RAS CRP CAS ASR V IH ADDR ROW IOH DQ V IOL TIMING PARAMETERS -5 SYMBOL MIN ...

Page 12

WRITE and READ-MODIFY-WRITE cycles RAS CRP V IH CAS ASR V IH ADDR ROW WE IOH DQ V IOL ...

Page 13

V IH RAS CSH t CRP V CAS RAD t ASR t RAH V IH ADDR V ROW OPEN OE# ...

Page 14

V IH RAS CSH t CRP V IH CAS RAD t ASR t RAH V IH ADDR ROW WE IOH DQ V IOL V IH ...

Page 15

WRITE and READ-MODIFY-WRITE cycles RAS CRP V IH CAS RAD t ASR t RAH V IH ADDR ROW WE RAC V IOH ...

Page 16

EDO-PAGE-MODE READ EARLY WRITE CYCLE V IH RAS CRP t RCD V IH CAS RAD t ASR t RAH V IH ADDR ROW WE IOH DQ OPEN ...

Page 17

V IH RAS CRP V CAS ASR V IH ADDR WE OE TIMING PARAMETERS -5 SYMBOL MIN MAX ...

Page 18

V IH RAS CRP V IH CAS ASR V IH ADDR RAS RPC CSR V IH CAS# ...

Page 19

V IH RAS CRP CAS ASR t RAH V IH ADDR ROW OE TIMING PARAMETERS -5 SYMBOL MIN MAX t AA ...

Page 20

RAS RPC CSR V IH CAS WRP TIMING PARAMETERS -5 SYMBOL MIN MAX t CHD 15 t ...

Page 21

PIN #1 INDEX .050 (1.27) TYP .600 (15.24) TYP .037 (0.94) MAX DAMBAR PROTRUSION SEATING PLANE 1. All dimensions in inches (millimeters) MAX or typical where noted. NOTE: 2. Package width and ...

Page 22

PIN #1 INDEX .050 (1.27) TYP 1. All dimensions in inches (millimeters) MAX or typical where noted. NOTE: 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 4 ...

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