ics8421002 Integrated Device Technology, ics8421002 Datasheet

no-image

ics8421002

Manufacturer Part Number
ics8421002
Description
Fiber Channel Low Jitter Xtal-input Hstl-output 212.5/ 106-mhz Clock Synthesizer
Manufacturer
Integrated Device Technology
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ics8421002AGI-01LF
Manufacturer:
IDT
Quantity:
24
G
the following frequencies can be generated based on the 2
frequency select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz,
159.375MHz, 106.25MHz and 53.125MHz. The ICS8421002I uses
IDT’s 3
achieve 1ps or lower typical rms phase jitter, easily meeting Fibre
Channel jitter requirements. The ICS8421002I is packaged in a
small 20-pin TSSOP package.
FEMTOCLOCKS™ CRYSTAL-TO-HSTL
FREQUENCY SYNTHESIZER
F
B
IDT
HiPerClockS™
nXTAL_SEL
IC S
REQUENCY
XTAL_OUT
F
F_SEL[1:0]
nPLL_SEL
REF_CLK
ENERAL
LOCK
e r
2
2
2
2
2
XTAL_IN
(
6
6
6
6
3
n I
/ ICS
M
q
5 .
5 .
5 .
5 .
4 .
p
u
H
rd
MR
6
6
6
6
3
t u
e
) z
2
2
2
2
7
n
generation low phase noise VCO technology and can
5
5
5
5
5
c
HSTL FREQUENCY SYNTHESIZER
26.5625MHz
Pulldown
Pulldown
Pulldown
Pulldown
y
Pulldown
D
S
The ICS8421002I is a 2 output HSTL Synthesizer
optimized to generate Fibre Channel reference clock
frequencies and is a member of the HiPerClocks
family of high performance clock solutions from IDT.
Using a 26.5625MHz 18pF parallel resonant crystal,
ELECT
IAGRAM
D
F
_
OSC
S
ESCRIPTION
0
0
0
1
1
E
F
L
UNCTION
1
F
_
1 1
0
S
0
0
0
1
1
T
E
ABLE
L
0
2
M
Detector
Phase
V
D
a
2
2
2
2
2
v i
u l
4
4
4
4
4
n I
d i
e
p
M = 24 (fixed)
r e
u
s t
N
V
D
a
VCO
1
v i
3
4
6
3
u l
2
d i
e
r e
D
v i
TM
1
0
d i
M
1
r e
8
6
4
2
8
N /
F
• Two HSTL outputs (VOHmax = 1.5V)
• Selectable crystal oscillator interface
• Supports the following output frequencies: 212.5MHz,
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
• Power supply modes:
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) an lead-free (RoHS 6)
V
a
or LVCMOS/LVTTL single-ended input
187.5MHz, 159.375MHz, 106.25MHz, 53.125MHz
(637kHz - 10MHz): 0.59ps (typical)
Core/Output
3.3V/1.8V
2.5V/1.8V
packages
EATURES
u l
F_SEL[1:0]
0 0
0 1
1 0
1 1
e
÷3
÷4
÷6
÷12
F
e r
(default)
1
O
1
5
(
2
5
1
M
q
0
3
u
1
9
8
6
1 .
u
p t
H
2
3 .
7
2 .
e
5 .
2
5 .
) z
t u
7
n
5
5
5
c
y
Q0
nQ0
Q1
nQ1
ICS8421002I REV B AUGUST 7, 2006
P
nPLL_SEL
6.5mm x 4.4mm x 0.92mm
IN
F_SEL0
V
V
nQ0
V
DDO
MR
DDA
Q0
A
ICS8421002I
nc
nc
20-Lead TSSOP
DD
ICS8421002I
SSIGNMENT
package body
G Package
Top View
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
Q1
nQ1
GND
V
nXTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
DD
DDO

Related parts for ics8421002

ics8421002 Summary of contents

Page 1

... The ICS8421002I uses rd IDT’s 3 generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Fibre Channel jitter requirements. The ICS8421002I is packaged in a small 20-pin TSSOP package ...

Page 2

... ICS8421002I REV B AUGUST 7, 2006 ...

Page 3

... ICS8421002I REV B AUGUST 7, 2006 µ A µ ...

Page 4

... ICS8421002I REV B AUGUST 7, 2006 ...

Page 5

... ICS8421002I REV B AUGUST 7, 2006 ...

Page 6

... Fibre Channel Filter to raw data 10k 100k FFSET REQUENCY 3.3V Z Fibre Channel Jitter Filter 212.5MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.59ps (typical) 1M 10M 100M @ 3.3V Z Fibre Channel Jitter Filter 53.125MHz RMS Phase Jitter (Random) 1M 10M 100M ) ICS8421002I REV B AUGUST 7, 2006 ...

Page 7

... Qx DDO V DDA HSTL nQx UTPUT OAD EST IRCUIT 80% 80% 20 ISE ALL IME Q0 PERIOD t PW odc = x 100% t PERIOD UTY YCLE ULSE IDTH ERIOD ICS8421002I REV B AUGUST 7, 2006 SCOPE 20% ...

Page 8

... F bypass capacitor should be connected to each RYSTAL NPUT NTERFACE The ICS8421002I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below 18pF Parallel Crystal ECOMMENDATIONS FOR NUSED I ...

Page 9

... Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8421002I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. ...

Page 10

... OL_MAX L DD_MAX OL_MAX Pd_H = (1V/ (2V - 1V) = 20mW Pd_L = (0.4V/ (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW IDT ™ / ICS ™ HSTL FREQUENCY SYNTHESIZER V DDO HSTL D C IGURE RIVER IRCUIT AND 10 V OUT ERMINATION load. ICS8421002I REV B AUGUST 7, 2006 ...

Page 11

... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS8421002I is: 2951 IDT ™ / ICS ™ HSTL FREQUENCY SYNTHESIZER R ...

Page 12

... ° Reference Document: JEDEC Publication 95, MO-153 ° ICS8421002I REV B AUGUST 7, 2006 ...

Page 13

... ICS8421002I REV B AUGUST 7, 2006 ° ° ° ° ...

Page 14

... ICS8421002I REV B AUGUST 7, 2006 ...

Page 15

... ICS8421002I FEMTOCLOCKS™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...

Related keywords