ics83056agi-01t Integrated Device Technology, ics83056agi-01t Datasheet

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ics83056agi-01t

Manufacturer Part Number
ics83056agi-01t
Description
Lvcmos-input Lvcmos-output 6 Bit 2 1 250-mhz Clock Mux
Manufacturer
Integrated Device Technology
Datasheet
1.ICS83056AGI-01T.pdf (13 pages)
G
The output has a V
1.8V, making the device ideal for use in voltage translation ap-
plications. An output enable pin places the output in
a high impedance state which may be useful for testing or
debug. Possible applications include systems with up to 6 trans-
ceivers which need to be independently set for different rates.
For example, a board may have six transceivers, each of which
need to be independently configured for 1 Gigabit Ethernet or
1 Gigabit Fibre Channel rates. Another possible application may
require the ports to be independently set for FEC (Forward Er-
ror Correction) or non-FEC rates. The device operates up to
250MHz and is packaged in a 20 TSSOP.
B
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product
characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifica-
tions without notice.
83056AGI-01
HiPerClockS™
ICS
LOCK
ENERAL
CLK0
CLK1
SEL0
SEL5
OE
D
ily of High Performance Clock Solutions from IDT.
The ICS83056I-01 has two selectable single-ended
clock inputs and six single-ended clock outputs.
The ICS83056I-01 is a 6-bit, 2:1, Single-ended Mul-
tiplexer and a member of the HiPerClockS™ fam-
Pulldown
Pulldown
Pullup
IAGRAM
D
Pulldown
Pulldown
ESCRIPTION
DDO
pin which may be set at 3.3V, 2.5V, or
0
1
0
1
PRELIMINARY
Q0
Q5
1
F
• 6-bit, 2:1 single-ended multiplexer
• Nominal output impedance: 15 (V
• Maximum output frequency: 250MHz
• Propagation delay: 2.5ns (typical)
• Input skew: 45ps (typical)
• Part-to-part skew: TBD
• Operating supply modes:
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS5) and lead-free (RoHS 6)
P
Additive phase jitter, RMS (12KHz - 20MHz):
0.07ps (typical)
V
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
packages
EATURES
IN
DD
/V
A
6.5mm x 4.4mm x 0.92mm package body
DDO
SSIGNMENT
SEL5
SEL4
CLK1
SEL3
GND
V
ICS83056I-01
V
S
20-Lead TSSOP
DDO
Q5
Q4
Q3
DD
INGLE
G Package
Top View
1
2
3
4
5
6
7
8
9
10
ICS83056I-01
-E
20
19
18
17
16
15
14
13
12
11
NDED
DDO
SEL0
Q0
V
GND
Q1
SEL1
CLK0
OE
Q2
SEL2
DDO
=3 .3V)
REV. A DECEMBER 20, 2007
M
6-B
ULTIPLEXER
IT
, 2:1,

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ics83056agi-01t Summary of contents

Page 1

... Pulldown SEL5 Pullup OE The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifica- tions without notice. 83056AGI-01 PRELIMINARY F EATURES • 6-bit, 2:1 single-ended multiplexer • ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Package Thermal Impedance, JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS T = -40°C 85° ...

Page 4

T 4C. LVCMOS/LVTTL DC C ABLE ...

Page 5

T 5B ABLE HARACTERISTICS ...

Page 6

T 5D ABLE HARACTERISTICS ...

Page 7

The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most ...

Page 8

P ARAMETER 1.65V± DDO LVCMOS GND -1.65V±5% 3.3V C /3. ORE UTPUT OAD 2.05V±5% 1.25V± DDO LVCMOS GND -1.25V±5% 3.3V C /2. ORE UTPUT OAD ...

Page 9

V DD CLK0, CLK1 2 V DDO 2 Q0: ROPAGATION ELAY CLKx Q0:Q5 t PD1 CLKy Q0:Q5 t PD2 I S NPUT KEW 83056AGI-01 PRELIMINARY 20% Clock Outputs UTPUT ISE ALL Q0:Q5 O ...

Page 10

ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains ...

Page 11

ACKAGE UTLINE UFFIX FOR T ABLE S Reference Document: JEDEC Publication 95, MO-153 83056AGI-01 PRELIMINARY TSSOP EAD ACKAGE IMENSIONS ...

Page 12

... C I While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications ...

Page 13

83056AGI-01 PRELIMINARY ...

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