ics83054i-01 Integrated Device Technology, ics83054i-01 Datasheet

no-image

ics83054i-01

Manufacturer Part Number
ics83054i-01
Description
4-bit, 2 1, Single-ended Multiplexer
Manufacturer
Integrated Device Technology
Datasheet
4-BIT, 2:1, SINGLE-ENDED MULTIPLEXER
B
IDT
G
put has a V
ing the device ideal for use in voltage translation applications. An
output enable pin places the output in a high impedance state
which may be useful for testing or debug. Possible applications
include systems with up to four transceivers which need to be
independently set for different rates. For example, a board may
have four transceivers, each of which need to be independently
configured for 1 Gigabit Ethernet or 1 Gigabit Fibre Channel rates.
Another possible application may require the ports to be inde-
pendently set for FEC (Forward Error Correction) or non-FEC
rates. The device operates up to 250MHz and is packaged in a
16 TSSOP.
HiPerClockS™
IC S
LOCK
ENERAL
/ ICS
SEL0
CLK0
CLK1
SEL3
OE
4-BIT, 2:1, SINGLE-ENDED MULTIPLEXER
DDO
D
The ICS83054I-01 is a 4-bit, 2:1, Single-ended Mul-
tiplexer and a member of the HiPerClockS™ family
of High Performance Clock Solutions from IDT. The
ICS83054I-01 has two selectable single-ended clock
inputs and four single-ended clock outputs. The out-
Pulldown
Pulldown
Pullup
IAGRAM
pin which may be set at 3.3V, 2.5V, or 1.8V, mak-
D
ESCRIPTION
Pulldown
Pulldown
0
1
0
1
Q0
Q3
1
F
• Four-bit, 2:1 single-ended multiplexer
• Nominal output impedance: 15
• Maximum output frequency: 250MHz
• Propagation delay: 3.2ns (maximum), V
• Input skew: 170ps (maximum), V
• Output skew: 90ps (maximum), V
• Part-to-part skew: 800ps (maximum), V
• Additive phase jitter, RMS at 155.52MHz, (12kHz – 20MHz):
• Operating supply modes:
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
0.18ps (typical)
V
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
packages
EATURES
DD
/V
DDO
P
4.4mm x 5.0mm x 0.92mm package body
IN
A
SSIGNMENT
CLK1
SEL3
SEL2
GND
V
V
DDO
ICS83054I-01
16-Lead TSSOP
Q3
Q2
DD
ICS83054I-01 REV. A February 20, 2009
G Package
Top View
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
(V
DD
DD
DDO
= V
SEL0
Q0
V
GND
Q1
SEL1
CLK0
OE
= V
ICS83054I-01
DDO
= 3.3V)
DD
DDO
DDO
DD
= V
= V
= 3.3V
= 3.3V
DDO
DDO
= 3.3V
= 3.3V

Related parts for ics83054i-01

ics83054i-01 Summary of contents

Page 1

... SINGLE-ENDED MULTIPLEXER G D ENERAL ESCRIPTION The ICS83054I- 4-bit, 2:1, Single-ended Mul tiplexer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The HiPerClockS™ ICS83054I-01 has two selectable single-ended clock inputs and four single-ended clock outputs. The out- put has a V pin which may be set at 3 ...

Page 2

... ICS83054I-01 REV. A February 20, 2009 ...

Page 3

... ICS83054I-01 REV. A February 20, 2009 85° ...

Page 4

... ICS83054I-01 REV. A February 20, 2009 µ A µ A µ A µ ...

Page 5

... ICS83054I-01 REV. A February 20, 2009 ...

Page 6

... ICS83054I-01 REV. A February 20, 2009 ...

Page 7

... Additive Phase Jitter (Random) 100k FFSET ROM ARRIER REQUENCY noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment 155.52MHz (12kHz - 20MHz) = 0.18ps (typical) 10M 100M ) Z ICS83054I-01 REV. A February 20, 2009 ...

Page 8

... C 3.3V C IRCUIT ORE Part 1 SCOPE Qx Qx Part IRCUIT ART TO 8 SCOPE Qx /2. UTPUT OAD EST IRCUIT 0.9V±0.1V V DDO Qx GND -0.9V±0.1V /1. UTPUT OAD EST IRCUIT V DDO 2 V DDO 2 tsk(pp) S ART KEW ICS83054I-01 REV. A February 20, 2009 SCOPE ...

Page 9

... ULSE IDTH ERIOD IDT ™ / ICS ™ 4-BIT, 2:1, SINGLE-ENDED MULTIPLEXER V 80 20% V DDO Clock 2 t Outputs UTPUT ISE ALL IME CLKx Q0:Q3 t PD1 CLKy Q0:Q3 t PD2 I S NPUT KEW 9 80% 20 tsk( – t PD2 PD1 ICS83054I-01 REV. A February 20, 2009 ...

Page 10

... ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS83054I-01 is: 967 IDT ™ / ICS ™ 4-BIT, 2:1, SINGLE-ENDED MULTIPLEXER A I PPLICATION NFORMATION O P NPUT AND UTPUT INS O UTPUTS LVCMOS O All unused LVCMOS output can be left floating ...

Page 11

... ° Reference Document: JEDEC Publication 95, MO-153 ° ICS83054I-01 REV. A February 20, 2009 ...

Page 12

... ICS83054I-01 REV. A February 20, 2009 ° ° ° ° ...

Page 13

... ICS83054I-01 4-BIT, 2:1, SINGLE-ENDED MULTIPLEXER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...

Related keywords