ics932s421

Manufacturer Part Numberics932s421
DescriptionPcie Gen 2 & Fbd Compliant Ck410b Ck410b+ Clock For Intel-based Servers
ManufacturerIntegrated Device Technology
ics932s421 datasheet
 


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Integrated
Circuit
Systems, Inc.
PCIe Gen 2 main Clock for Intel-based Servers
Recommended Application:
PCIe Gen 2 & FBD compliant CK410B (CK410B+) clock for
Intel-based servers
Output Features:
4 - 0.7V current-mode differential CPU pairs
5 - 0.7V current-mode differential SRC pair
4 - PCI (33MHz)
3 - PCICLK_F, (33MHz) free-running
1 - 48MHz
2 - REF, 14.318MHz
Features/Benefits:
Supports spread spectrum modulation, 0 to -0.5% down
spread
Uses external 14.318MHz crystal and external load
capacitors for low ppm synthesis error
CPU clocks independent of SRC/PCI clocks
D2/D3 SMBus address
Functionality
CPU
SRC
1
1
2
FS_C
FS_B
FS_A
MHz
MHz
0
0
0
266.67 100.00
0
0
1
133.33 100.00
0
1
0
200.00 100.00
0
1
1
166.67 100.00
1
0
0
333.33 100.00
1
0
1
100.00 100.00
1
1
0
400.00 100.00
1
1
1
1. FS_B and FS_C are three-level inputs. Please see V
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_A is a low-threshold input. Please see the V
IL_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
1340B—06/13/07
Key Specifications:
PCIe Gen 2 compliant SRC outputs
FBD 2 compliant CPU clocks
CPU cycle-cycle jitter: < 50ps
SRC cycle-cycle jitter: < 125ps
PCI cycle-cycle jitter: < 500ps
CPU output skew: < 50ps
SRC output skew: < 250ps
± 300ppm frequency accuracy on all outputs except
48MHz
± 100ppm frequency accuracy on 48MHz
Pin Configuration
PCI
REF
U
SB
MHz
MHz
MHz
33.33 14.318
48.000
PCICLK0 3
33.33 14.318
48.000
PCICLK1 4
33.33 14.318
48.000
PCICLK2 5
33.33 14.318
48.000
PCICLK3 6
33.33 14.318
48.000
33.33 14.318
48.000
33.33 14.318
48.000
Reserved
PCICLK_F0 9
and V
specifications in
PCICLK_F1 10
IL_FS
IH_FS
PCICLK_F2 11
and V
IH_FS
VDDSRC 15
SRCCLKT0 16
SRCCLKC0 17
SRCCLKC1 18
SRCCLKT1 19
GNDSRC 20
SRCCLKT2 21
SRCCLKC2 22
SRCCLKC3 23
SRCCLKT3 24
VDDSRC 25
SRCCLKT4 26
SRCCLKC4 27
VDDSRC 28
ICS932S421B
VDDPCI 1
56 FS_C/TEST_SEL
GNDPCI 2
55 REF0
54 REF1
53 VDDREF
52 X1
51 X2
GNDPCI 7
50 GNDREF
VDDPCI 8
49 FS_B/TEST_MODE
48 FS_A
47 VDDCPU
46 CPUCLKT0
VDD48 12
45 CPUCLKC0
48MHz 13
44 VDDCPU
GND48 14
43 CPUCLKT1
42 CPUCLKC1
41 GNDCPU
40 CPUCLKT2
39 CPUCLKC2
38 VDDCPU
37 CPUCLKT3
36 CPUCLKC3
35 VDDA
34 GNDA
33 IREF
32 NC
31 Vtt_PwrGd#/PD
30 SDATA
29 SCLK
56-pin SSOP & TSSOP

ics932s421 Summary of contents

  • Page 1

    ... IH_FS PCICLK_F2 11 and V IH_FS VDDSRC 15 SRCCLKT0 16 SRCCLKC0 17 SRCCLKC1 18 SRCCLKT1 19 GNDSRC 20 SRCCLKT2 21 SRCCLKC2 22 SRCCLKC3 23 SRCCLKT3 24 VDDSRC 25 SRCCLKT4 26 SRCCLKC4 27 VDDSRC 28 ICS932S421B VDDPCI 1 56 FS_C/TEST_SEL GNDPCI 2 55 REF0 54 REF1 53 VDDREF GNDPCI 7 50 GNDREF VDDPCI 8 49 FS_B/TEST_MODE 48 FS_A 47 VDDCPU 46 CPUCLKT0 VDD48 12 45 CPUCLKC0 ...

  • Page 2

    ... Complement clock of differential SRC clock pair. OUT True clock of differential SRC clock pair. PWR Supply for SRC clocks, 3.3V nominal OUT True clock of differential SRC clock pair. OUT Complement clock of differential SRC clock pair. PWR Supply for SRC clocks, 3.3V nominal 2 ICS932S421B DESCRIPTION ...

  • Page 3

    ... OUT 14.318 MHz reference clock. OUT 14.318 MHz reference clock. 3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see input electrical characteristics for Vil_FS and Vih_FS values. IN TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table 3 ICS932S421B ...

  • Page 4

    ... Systems, Inc. General Description ICS932S421B is a main clock synthesizer for CK410B-generation Intel server platforms. ICS932S421B is driven with a 14.318MHz crystal. It generates CPU outputs up to 400MHz and PCI-Express clocks at 100. The 48 MHz USB clock is an exact 48.000 MHz clock. The ICS932S421B generates all other clocks with less the +/- 300 ppm error. ...

  • Page 5

    ... PD# rise time of PD# rise time of Max. Voltage on SCLK/SDAT Max. Voltage on SCLK/SDAT @ PULLUP PULLUP 4 4 (Max VIL - 0.15) to (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) (Min VIH + 0.15) to (Min VIH + 0.15) to (Max VIL - 0.15) (Max VIL - 0.15) 5 ICS932S421B TYP TYP MAX MAX UNITS NOTES UNITS NOTES 0 0.8 0 ...

  • Page 6

    ... V = 0.175V 0.525V 0.525V V = 0.175V OH OL Measurement from differential wavefrom CPU (3: 50% T Measurement from differential wavefrom 6 ICS932S421B MIN TYP MAX UNITS Ω 3000 660 850 mV -150 150 1150 mV -300 250 550 mV 140 mV -300 300 ppm 2 ...

  • Page 7

    ... SSC removed) PCIe2Lo from 1.5MHz-Nyquist both using the Gen2 θ PCIe2Hi difference function (including PLL BW 11 0.54, θ FBD Td=5 ns, Ftrk=0.2 MHz) 7 ICS932S421B = 475Ω REF MIN TYP MAX UNITS NOTES 3000 660 850 -150 150 1150 ...

  • Page 8

    ... Nominal V @ MIN = 1 MAX = 3.135 @MIN = 1. MAX = ICS932S421B MIN TYP MAX UNITS -300 0.00 300 ppm 29.99100 30.00900 ns 29.99100 30.15980 ns 29.49100 30.50900 ns 29.49100 30.65980 N/A ns 2.4 V 0.55 V -33 ...

  • Page 9

    ... OL V @MIN = 1 @MAX = 3.135 @MIN = 1. @MAX = ICS932S421B MIN TYP MAX UNITS NOTES -300 0 300 ppm 69.82033 69.86224 ns 68.82033 70.86224 ns 2.4 V 0.4 V - 500 ps ...

  • Page 10

    ... Suggested termination resistors are as follows for transmission lines with ohms: Single-ended outputs at 2-load strength (Power up default for all single-ended outputs) Single-ended outputs at 1-load strength (REF clock only) 1340B—06/13/ Test Load Driving 1 load ohms Driving 2 loads 7.5 ohms Driving 1 load ohms 10 ICS932S421B CL=5pF CL=5pF CL=5pF ...

  • Page 11

    ... Integrated Circuit Systems, Inc. General SMBus serial interface information for the ICS932S421B How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • ...

  • Page 12

    ... Control Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Name Control Function Free-Running Control, Default: not affected by PCI/SRC_STOP (Byte 4, bit 5) 12 ICS932S421B Type Disable-Hi-Z Enable RW Disable-Hi-Z Enable RW Disable-Hi-Z Enable RW Disable-Hi-Z Enable ...

  • Page 13

    ... RESERVED Stop non-free running PC and SRC clocks. FS_C readback FS_C FS_B readback FS_B FS_A readback FS_A Name Control Function RID3 RID2 REVISION ID RID1 RID0 VID3 VID2 VENDOR ID VID1 VID0 13 ICS932S421B Type Driven Hi-Z RW Driven Hi-Z RW Driven Hi-Z RW Driven Hi-Z RW Free-Running Stoppable RW Free-Running Stoppable RW ...

  • Page 14

    ... PCI = 32 MHz Nominal) Only active if Byte 10, bit Set alternate CPU frequency: 166 MHz to 160 MHz MHz. 333 MHz to 320 MHz ICS932S421B Type Writing to this register will RW configure how many bytes will RW be read back, default bytes ...

  • Page 15

    ... Byte12 bit(7:0) and Byte11 bit(7:6) Name Control Function Spread Spectrum Programming bit(7:0) Name Control Function Reserved Spread Spectrum Programming bit(14:8) 15 ICS932S421B Type The decimal representation and N Divider in Byte 11 and RW 12 will configure the CPU VCO RW frequency. Default at power up = latch-in or Byte 0 Rom RW table ...

  • Page 16

    ... Name Control Function N Divider Programming b(7:0) Name Control Function Spread Spectrum Programming b(7:0) Name Control Function Reserved Spread Spectrum Programming b(14:8) 16 ICS932S421B Type The decimal representation and N Divider in Byte 15 and RW 16 will configure the SRC VCO RW frequency. Default at power up = latch-in or Byte 0 Rom RW table ...

  • Page 17

    ... Programming Bits Test Function ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST 17 ICS932S421B Type See CPU, SRC and PCI Divider Ratios Table RW RW Type ...

  • Page 18

    ... REF1 REF0 ICS932S421B ...

  • Page 19

    ... ICS932S421B ...

  • Page 20

    ... Tstable <1.8mS Tdrive_PwrDwn# <300µS, >200mV HW TEST ENTRY FS_C/TEST FS_B/TEST _SEL _MODE HW PIN HW PIN ICS932S421B SW REF/N or BIT HI-Z B6b6 B6b7 OUTPUT 0 X NORMAL REF REF REF HI REF/N ...

  • Page 21

    ... SEATING SEATING PLANE PLANE .10 (.004) C .10 (.004) C Designation for tape and reel packaging Annealed Lead Free (optional) Package Type F = SSOP Revision Designator Device Type Prefix ICS = Standard Device 21 ICS932S421B In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN 2.41 2.80 .095 0.20 0.40 .008 0.20 0.34 ...

  • Page 22

    ... PLANE PLANE aaa C Designation for tape and reel packaging Annealed Lead Free (optional) Package Type G = TSSOP Revision Designator Device Type Prefix ICS = Standard Device 22 ICS932S421B 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN -- 1.20 -- 0.05 ...

  • Page 23

    ... Initial Release 1. Added/Changed descriptions on page 1. 2. Added PLL Phase Jitter Impact Table. 0.2 11/15/06 3. Corrected PD timing diagram & descriptions. 4. Removed typical values pending characterization A 04/26/07 1. Updated Single-ended Output Terminations. 2. Release to Final. B 06/13/07 1. Updated CPU output numbers on the block diagram. 1340B—06/13/07 23 ICS932S421B Page # - 1, 7, 19- ...