ics932s421b Integrated Device Technology, ics932s421b Datasheet
ics932s421b
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ics932s421b Summary of contents
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... SRCCLKT2 21 36 CPUCLKC3 SRCCLKC2 22 35 VDDA SRCCLKC3 23 34 GNDA SRCCLKT3 24 33 IREF VDDSRC SRCCLKT4 26 31 Vtt_PwrGd#/PD SRCCLKC4 27 30 SDATA VDDSRC 28 29 SCLK 56-pin SSOP & TSSOP ICS932S421B CPU SRC PCI REF 2 FS_A MHz MHz MHz MHz 0 266.67 1 133.33 0 200.00 100.00 33 ...
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... Complement clock of differential SRC clock pair. OUT True clock of differential SRC clock pair. PWR Supply for SRC clocks, 3.3V nominal OUT True clock of differential SRC clock pair. OUT Complement clock of differential SRC clock pair. PWR Supply for SRC clocks, 3.3V nominal 2 ICS932S421B DESCRIPTION ...
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... OUT 14.318 MHz reference clock. OUT 14.318 MHz reference clock. 3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see input electrical characteristics for Vil_FS and Vih_FS values. IN TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table 3 ICS932S421B ...
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... Systems, Inc. General Description ICS932S421B is a main clock synthesizer for CK410B-generation Intel server platforms. ICS932S421B is driven with a 14.318MHz crystal. It generates CPU outputs up to 400MHz and PCI-Express clocks at 100. The 48 MHz USB clock is an exact 48.000 MHz clock. The ICS932S421B generates all other clocks with less the +/- 100 ppm error. ...
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... Suggested termination resistors are as follows for transmission lines with ohms: Single-ended outputs at 2-load strength (Power up default for all single-ended outputs) Single-ended outputs at 1-load strength (REF clock only) 1340D—11/20/ Test Load Driving 1 load ohms Driving 2 loads 7.5 ohms Driving 1 load ohms 5 ICS932S421B CL=5pF CL=5pF CL=5pF ...
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... From VDD Power-Up or de- assertion 1st clock Triangular Modulation 30 CPU output enable after PD de-assertion PD fall time of PD rise time of 2 PULLUP 4 (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 6 ICS932S421B TYP MAX UNITS ° 150 C 70 °C 115 ° ...
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... VOH = 0.525V VOL = 0.175V 175 VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V Measurement from differential 45 waveform VT = 50% Measurement from differential waveform =49.9 P REF = and REF ICS932S421B TYP MAX UNITS NOTES Ω 1 850 mV 1,3 150 mV 1,3 1150 550 mV 1 140 mV ...
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... MIN = 1. MAX = 0 Rising/Falling edge rate 0 2 0 ICS932S421B TYP MAX UNITS NOTES 100 ppm 1,2 30 30.0030 ns 30.5030 ns 30.07519 30.0852 30.5852 ns 2,3 ns N ...
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... MIN = 1. MAX = 0 USB48 Rising/Falling edge rate ICS932S421B TYP MAX UNITS NOTES 0 ppm 1,2 20.83333 20.8333 ns 21.1833 10.036 9.836 ...
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... 1 Conditions Min PCIe Gen 1 PCIe Gen 2 10kHz < f < 1.5MHz PCIe Gen 2 1.5MHz < f < Nyquist (50MHz) FBD1 3.2/4G 11MHz to 33MHz FBD1 4.8G 11MHz to 33MHz QPI 133MHz 6.4GB_12UI CPU outputs only 10 ICS932S421B TYP MAX UNITS Notes 0 100 ppm 1,2 69.84128 69.8483 ns 70.8483 ns ns N/A N 0.4 ...
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... ICS932S421B ppm ps % 0.1s 1us 1 Clock + ppm +SSC +c2c jitter Long-Term Short-Term AbsPer Average Average Max Max Max 10.00100 10.05100 7.50075 7.55075 6 ...
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... Integrated Circuit Systems, Inc. General SMBus serial interface information for the ICS932S421B How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends the beginning byte location = N • ICS clock will acknowledge • ...
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... Control Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Name Control Function Free-Running Control, Default: not affected by PCI/SRC_STOP (Byte 4, bit 5) 13 ICS932S421B Type Disable-Hi-Z Enable RW Disable-Hi-Z Enable RW Disable-Hi-Z Enable RW Disable-Hi-Z Enable ...
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... RESERVED Stop non-free running PC and SRC clocks. FS_C readback FS_C FS_B readback FS_B FS_A readback FS_A Name Control Function RID3 RID2 REVISION ID RID1 RID0 VID3 VID2 VENDOR ID VID1 VID0 14 ICS932S421B Type Driven Hi-Z RW Driven Hi-Z RW Driven Hi-Z RW Driven Hi-Z RW Free-Running Stoppable RW Free-Running Stoppable RW ...
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... PCI = 32 MHz Only active if Byte 10, bit Set alternate CPU frequency: 166 MHz to 160 MHz MHz. 333 MHz to 320 MHz ICS932S421B Type Writing to this register will RW configure how many bytes will RW be read back, default bytes ...
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... Byte12 bit(7:0) and Byte11 bit(7:6) Name Control Function Spread Spectrum Programming bit(7:0) Name Control Function Reserved Spread Spectrum Programming bit(14:8) 16 ICS932S421B Type The decimal representation of M and N Divider in Byte 11 and RW 12 will configure the CPU VCO RW frequency. Default at power latch-in or Byte 0 Rom table ...
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... Control Function N Divider Programming b(7:0) Name Control Function Spread Spectrum Programming b(7:0) Name Control Function Reserved Spread Spectrum Programming b(14:8) 17 ICS932S421B Type The decimal representation of M and N Divider in Byte 15 and RW 16 will configure the SRC VCO RW frequency. Default at power latch-in or Byte 0 Rom table. ...
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... Programming Bits Test Function ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST 18 ICS932S421B Type See CPU, SRC and PCI Divider Ratios Table RW RW Type ...
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... ICS932S421B REF Drive Strength Functionality Byte6, Byte Byte 10, ...
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... B6b7: 1= REF/N, Default = 0 (HI-Z) 1340D—11/20/08 Tstable <1.8mS Tdrive_PwrDwn# <300µS, >200mV HW ENTRY FS_C/TEST FS_B/TEST _SEL _MODE HW PIN HW PIN ICS932S421B SW TEST REF/N or BIT HI-Z B6b6 B6b7 OUTPUT 0 X NORMAL REF REF REF HI ...
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... C .10 (.004) C Designation for tape and reel packaging Annealed Lead Free (optional) Package Type F = SSOP Revision Designator Device Type Prefix ICS = Standard Device (not part of orderable part number) 21 ICS932S421B In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN 2.41 2.80 .095 ...
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... Designation for tape and reel packaging Annealed Lead Free (optional) Package Type G = TSSOP Revision Designator Device Type Prefix ICS = Standard Device (not part of orderable part number) 22 ICS932S421B 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX ...
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... Revision History Rev. Issue Date Description A 4/26/2007 1. Updated Single-ended Output Terminations. 2. Release to Final. B 6/13/2007 1. Updated CPU output numbers on the block diagram. C 9/17/2008 Updated electrical characteristics, PPM and clock period data D 11/20/2008 Added 48MHz electrical char table. 1340D—11/20/08 23 ICS932S421B Page # 10 4 Various 9 ...