ics932s421c

Manufacturer Part Numberics932s421c
DescriptionPcie Gen 2 And Qpi Clock For Intel-based Servers
ManufacturerIntegrated Device Technology
ics932s421c datasheet
 


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Integrated
Circuit
Systems, Inc.
PCIe Gen 2 and QPI Clock for Intel-based Servers
Recommended Application:
PCIe Gen 2 & QPI compliant CK410B+ clock for Intel-based
servers
Output Features:
4 - 0.7V current-mode differential CPU pairs
5 - 0.7V current-mode differential SRC pair
4 - PCI (33MHz)
3 - PCICLK_F, (33MHz) free-running
1 - 48MHz
2 - REF, 14.318MHz
Features/Benefits:
Supports spread spectrum modulation, 0 to -0.5%
down spread
Uses external 14.318MHz crystal and external load
capacitors for low ppm synthesis error
CPU clocks independent of SRC/PCI clocks
D2/D3 SMBus address
Increased CPU amplitude at higher speeds compared
to 932S421B
Pin Configuration
1460E—08/25/09
Key Specifications:
PCIe Gen 2 compliant SRC outputs
QPI & FBD 2 compliant CPU clocks
CPU cycle-cycle jitter: < 50ps
SRC cycle-cycle jitter: < 125ps
PCI cycle-cycle jitter: < 500ps
CPU output skew: < 50ps
SRC output skew: < 250ps
± 100ppm frequency accuracy on all outputs
Functionality
1
1
FS_C
FS_B
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
1. FS_B and FS_C are three-level inputs. Please see V
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_A is a low-threshold input. Please see the V
specifications in the Input/Supply/Common Output Parameters Table for correct values.
VDDPCI 1
56 FS_C/TEST_SEL
GNDPCI 2
55 REF0
PCICLK0 3
54 REF1
PCICLK1 4
53 VDDREF
PCICLK2 5
52 X1
PCICLK3 6
51 X2
GNDPCI 7
50 GNDREF
VDDPCI 8
49 FS_B/TEST_MODE
PCICLK_F0 9
48 FS_A
PCICLK_F1 10
47 VDDCPU
PCICLK_F2 11
46 CPUCLKT0
VDD48 12
45 CPUCLKC0
48MHz 13
44 VDDCPU
GND48 14
43 CPUCLKT1
VDDSRC 15
42 CPUCLKC1
SRCCLKT0 16
41 GNDCPU
SRCCLKC0 17
40 CPUCLKT2
SRCCLKC1 18
39 CPUCLKC2
SRCCLKT1 19
38 VDDCPU
GNDSRC 20
37 CPUCLKT3
SRCCLKT2 21
36 CPUCLKC3
SRCCLKC2 22
35 VDDA
SRCCLKC3 23
34 GNDA
SRCCLKT3 24
33 IREF
VDDSRC 25
32 NC
SRCCLKT4 26
31 Vtt_PwrGd#/PD
SRCCLKC4 27
30 SDATA
VDDSRC 28
29 SCLK
56-pin SSOP & TSSOP
ICS932S421C
CPU
SRC
PCI
REF
2
FS_A
MHz
MHz
MHz
MHz
0
266.67
1
133.33
0
200.00
1
166.67
100.00
33.33
14.32
0
333.33
1
100.00
0
400.00
1
Reserved
and V
specifications in
IL_FS
IH_FS
and V
IL_FS
IH_FS
U
SB
MHz
48.00

ics932s421c Summary of contents

  • Page 1

    ... CPUCLKT3 SRCCLKT2 21 36 CPUCLKC3 SRCCLKC2 22 35 VDDA SRCCLKC3 23 34 GNDA SRCCLKT3 24 33 IREF VDDSRC SRCCLKT4 26 31 Vtt_PwrGd#/PD SRCCLKC4 27 30 SDATA VDDSRC 28 29 SCLK 56-pin SSOP & TSSOP ICS932S421C CPU SRC PCI REF 2 FS_A MHz MHz MHz MHz 0 266.67 1 133.33 0 200.00 1 166 ...

  • Page 2

    ... Complementary clock of differential SRC clock pair. OUT True clock of differential SRC clock pair. PWR Supply for SRC clocks, 3.3V nominal OUT True clock of differential SRC clock pair. OUT Complementary clock of differential SRC clock pair. PWR Supply for SRC clocks, 3.3V nominal 2 ICS932S421C DESCRIPTION ...

  • Page 3

    ... MHz reference clock. OUT 14.318 MHz reference clock. 3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see input electrical characteristics for Vil_FS and Vih_FS values. IN TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table 3 ICS932S421C Pin Description ...

  • Page 4

    ... Systems, Inc. General Description The ICS932S421C is a main clock synthesizer for CK410B+ generation Intel server platforms. The ICS932S421C is driven with a 14.318MHz crystal. It generates CPU outputs up to 400MHz and PCI-Express clocks at 100 or 200 MHz. The 48 MHz USB clock is an exact 48.000 MHz clock. ...

  • Page 5

    ... Suggested termination resistors are as follows for transmission lines with ohms: Single-ended outputs at 2-load strength (Power up default for all single-ended outputs) Single-ended outputs at 1-load strength (REF clock only) 1460E—08/25/ Test Load Driving 1 load ohms Driving 2 loads 7.5 ohms Driving 1 load ohms 5 ICS932S421C CL=5pF CL=5pF CL=5pF ...

  • Page 6

    ... From VDD Power-Up or de- assertion 1st clock Triangular Modulation 30 CPU output enable after PD de-assertion PD fall time of PD rise time of 2 PULLUP 4 (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 6 ICS932S421C TYP MAX UNITS ° 150 C 70 °C 115 ° ...

  • Page 7

    ... VOH = 0.525V VOL = 0.175V 175 VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V Measurement from differential 45 waveform VT = 50% Measurement from differential waveform =49.9 P REF = and REF ICS932S421C TYP MAX UNITS NOTES Ω 1 850 mV 1,3 150 mV 1,3 1150 550 mV 1 140 mV ...

  • Page 8

    ... MIN = 1. MAX = 0 Rising/Falling edge rate 0 2 0 ICS932S421C TYP MAX UNITS NOTES 100 ppm 1,2 30 30.0030 ns 30.5030 ns 30.07519 30.0852 30.5852 ns 2,3 ns N ...

  • Page 9

    ... MIN = 1. MAX = 0 USB48 Rising/Falling edge rate ICS932S421C TYP MAX UNITS NOTES 0 ppm 1,2 20.83333 20.8333 ns 21.1833 10.036 9.836 ...

  • Page 10

    ... 1 Conditions Min PCIe Gen 1 PCIe Gen 2 10kHz < f < 1.5MHz PCIe Gen 2 1.5MHz < f < Nyquist (50MHz) FBD1 3.2/4G 11MHz to 33MHz FBD1 4.8G 11MHz to 33MHz QPI 133MHz 6.4GB_12UI CPU outputs only 10 ICS932S421C TYP MAX UNITS Notes 0 100 ppm 1,2 69.84128 69.8483 ns 70.8483 ns ns N/A N 0.4 ...

  • Page 11

    ... ICS932S421C ppm ps % 0.1s 1us 1 Clock + ppm +SSC +c2c jitter Long-Term Short-Term AbsPer Average Average Max Max Max 10.00100 10.05100 7.50075 7.55075 6 ...

  • Page 12

    ... Integrated Circuit Systems, Inc. General SMBus serial interface information for the ICS932S421C How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends the beginning byte location = N • ICS clock will acknowledge • ...

  • Page 13

    ... Control Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Name Control Function Free-Running Control, Default: not affected by PCI/SRC_STOP (Byte 6, bit 3) 13 ICS932S421C Type Disable-Hi-Z Enable RW Disable-Hi-Z Enable RW Disable-Hi-Z Enable RW Disable-Hi-Z Enable ...

  • Page 14

    ... RESERVED Stop non-free running PC and SRC clocks. FS_C readback FS_C FS_B readback FS_B FS_A readback FS_A Name Control Function RID3 RID2 REVISION ID RID1 RID0 VID3 VID2 VENDOR ID VID1 VID0 14 ICS932S421C Type Driven Hi-Z RW Driven Hi-Z RW Driven Hi-Z RW Driven Hi-Z RW Free-Running Stoppable RW Free-Running Stoppable RW ...

  • Page 15

    ... PCI = 32 MHz Only active if Byte 10, bit Set alternate CPU frequency: 166 MHz to 160 MHz MHz. 333 MHz to 320 MHz ICS932S421C Type Writing to this register will RW configure how many bytes will RW be read back, default bytes ...

  • Page 16

    ... Byte12 bit(7:0) and Byte11 bit(7:6) Name Control Function Spread Spectrum Programming bit(7:0) Name Control Function Reserved Spread Spectrum Programming bit(14:8) 16 ICS932S421C Type The decimal representation of M and N Divider in Byte 11 and RW 12 will configure the CPU VCO RW frequency. Default at power latch-in or Byte 0 Rom table ...

  • Page 17

    ... Control Function N Divider Programming b(7:0) Name Control Function Spread Spectrum Programming b(7:0) Name Control Function Reserved Spread Spectrum Programming b(14:8) 17 ICS932S421C Type The decimal representation of M and N Divider in Byte 15 and RW 16 will configure the SRC VCO RW frequency. Default at power latch-in or Byte 0 Rom table. ...

  • Page 18

    ... Programming Bits Test Function ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST ICS ONLY TEST 18 ICS932S421C Type See CPU, SRC and PCI Divider Ratios Table RW RW Type ...

  • Page 19

    ... ICS932S421C REF Drive Strength Functionality Byte6, Byte Byte 10, ...

  • Page 20

    ... B6b7: 1= REF/N, Default = 0 (HI-Z) 1460E—08/25/09 Tstable <1.8mS Tdrive_PwrDwn# <300µS, >200mV HW ENTRY FS_C/TEST FS_B/TEST _SEL _MODE HW PIN HW PIN ICS932S421C SW TEST REF/N or BIT HI-Z B6b6 B6b7 OUTPUT 0 X NORMAL REF REF REF HI ...

  • Page 21

    ... VARIATIONS N 56 Reference Doc.: JEDEC Publication 95, MO-118 - 10-0034 SEATING SEATING PLANE PLANE .10 (.004) C .10 (.004 ICS932S421C In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN 2.41 2.80 .095 0.20 0.40 .008 0.20 0.34 .008 0.13 0.25 .005 SEE VARIATIONS SEE VARIATIONS 10.03 10.68 .395 7 ...

  • Page 22

    ... Reference Doc.: JEDEC Publication 95, MO-153 SEATING SEATING 10-0039 PLANE PLANE aaa C Package Tubes 56-pin SSOP 56-pin SSOP Tubes 56-pin TSSOP 56-pin TSSOP 22 ICS932S421C 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN -- 1.20 -- 0.05 0.15 .002 0.80 1.05 .032 ...

  • Page 23

    ... Updated electrical characteristics, PPM and clock period data C 11/20/2008 Added 48MHz electrical char table. Corrected Byte 10 bits 4 and 5 to reserved. For non-spread PCIe D 6/9/2009 applications see the 932S431. 1. Updated Byte 3 table. E 8/25/2009 2. Added new ordering info table. 1460E—08/25/09 23 ICS932S421C Page # - Various 9 15 Various ...