pc48f4400p0vt00 Intel Corporation, pc48f4400p0vt00 Datasheet
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Intel StrataFlash (P30) 1-Gbit P30 Family Product Features High performance — 85/88 ns initial access — 40 MHz with zero wait states clock-to- data output synchronous-burst read mode — asynchronous-page read mode — 4-, 8-, 16-, ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © 2005, Intel Corporation * Other names and brands may be claimed as the property of others. April 2005 ...
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Contents 1.0 Introduction ...............................................................................................................................7 1.1 Nomenclature .......................................................................................................................7 1.2 Acronyms ..............................................................................................................................7 1.3 Conventions..........................................................................................................................8 2.0 Functional Overview 3.0 Package Information 3.1 56-Lead TSOP Package .....................................................................................................10 3.2 64-Ball Easy BGA Package ................................................................................................12 3.3 QUAD+ SCSP Packages....................................................................................................13 4.0 Ballout and Signal Descriptions 4.1 Signal ...
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P30 Family 10.0 Read Operations .................................................................................................................... 53 10.1 Asynchronous Page-Mode Read........................................................................................ 53 10.2 Synchronous Burst-Mode Read.......................................................................................... 53 10.3 Read Configuration Register .............................................................................................. 54 10.3.1 Read Mode ............................................................................................................ 55 10.3.2 Latency Count........................................................................................................ 55 10.3.3 WAIT Polarity......................................................................................................... 57 10.3.4 Data Hold............................................................................................................... ...
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CFI Query ...........................................................................................................................77 Appendix A Write State Machine Appendix B Flowcharts Appendix C Common Flash Interface Appendix D Additional Information Appendix E Ordering Information for Discrete Products Appendix F Ordering Information for SCSP Products Datasheet Intel StrataFlash ..........................................................................................78 ............................................................................................................85 ...
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P30 Family Revision History Revision Date Revision April 2005 -001 April 2005 Intel StrataFlash 6 Initial Release ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Description Datasheet ...
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Introduction This document provides information about the Intel StrataFlash® Embedded Memory (P30) device and describes its features, operation, and specifications. 1.1 Nomenclature Block : Main block : Parameter block : ...
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P30 Family RFU : SR : WSM : 1.3 Conventions VCC : SR[4] : A[15: Bit : Byte : Word : Kbit : KByte : KWord : Mbit : ...
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Functional Overview This section provides an overview of the features and capabilities of the 1-Gbit P30 Family device. The P30 family provides density upgrades from 64-Mbit through 1-Gbit. This family of devices provides high performance at low voltage on ...
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P30 Family 3.0 Package Information 3.1 56-Lead TSOP Package Figure 1. TSOP Mechanical Specifications Z See Notes 1 and 3 Pin 1 See Detail A Detail A Table 1. TSOP Package Dimensions (Sheet Product Information Package ...
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Table 1. TSOP Package Dimensions (Sheet Product Information Terminal Dimension Lead Tip Length Lead Count Lead Tip Angle Seating Plane Coplanarity Lead to Package Offset Datasheet Intel StrataFlash Millimeters Sym Min Nom D 19.800 20.00 L 0.500 ...
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P30 Family 3.2 64-Ball Easy BGA Package Figure 2. Easy BGA Mechanical Specifications Ball A1 Corner Top View - Ball side down A1 A2 ...
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QUAD+ SCSP Packages Figure 3. 64/128-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x10x1.2 mm) A1 Index Mark Top View - Ball Down ...
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P30 Family Figure 4. 256-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.0 mm Index Mark Top View - Ball Down A2 N ...
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Figure 5. 512-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.2 mm Index Mark Top View - Ball Down A2 Dimensions Package Height ...
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P30 Family Figure 6. 1-Gbit, 88-ball (80 active) QUAD+ SCSP Specifications (11x11x1.4 mm) A1 Index Mark Top View - Ball Down A2 Dimens ions ...
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Ballout and Signal Descriptions 4.1 Signal Ballout Figure 7. 56-Lead TSOP Pinout (64/128/256-Mbit A15 A14 A13 A12 A11 A10 A9 A23 10 A22 11 A21 12 VSS 13 VCC 14 WE# 15 WP# 16 A20 17 A19 ...
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P30 Family Figure 8. 64-Ball Easy BGA Ballout (64/128/256/512-Mbit VSS DQ8 DQ1 DQ9 F RFU DQ0 DQ10 G A23 RFU DQ2 H RFU VSS VCC ...
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Figure 9. 88-Ball (80-Active Ball) QUAD+ SCSP Ballout Pin ...
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P30 Family 4.2 Signal Descriptions This section has signal descriptions for the various P30 packages. Table 3. TSOP and Easy BGA Signal Descriptions (Sheet Symbol Type ADDRESS INPUTS: Device address inputs. 64-Mbit: A[22:1]; 128-Mbit: A[23:1]; 256-Mbit: ...
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Table 3. TSOP and Easy BGA Signal Descriptions (Sheet Symbol Type VCCQ Power Output Power Supply: Output-driver source voltage. VSS Power Ground: Connect to system ground. Do not float any VSS connection. Reserved for Future Use: Reserved ...
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P30 Family Table 4. QUAD+ SCSP Signal Descriptions (Sheet Symbol Type WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock- WP# Input down cannot be unlocked with the Unlock command. WP# ...
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Figure 10. 512-Mbit Easy BGA Device Block Diagram F1-CE# A[MAX:1] Figure 11. 512-Mbit QUAD+ SCSP Device Block Diagram Figure 12. 1-Gbit QUAD+ SCSP Device Block Diagram F1-CE# WP# OE# WE# CLK ADV# A[MAX:0] Datasheet Intel StrataFlash Easy BGA 2-Die (512-Mbit) ...
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P30 Family 4.4 Memory Maps Table 7 through Table 10 Operations” on page 61 Table 7. Discrete Top Parameter Memory Maps (all packages) Programming Size Blk 256-Mbit Region # (KB) 32 258 FFC000 - FFFFFF 32 255 FF0000 - ...
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Table 7. Discrete Top Parameter Memory Maps (all packages) Programming Size Blk 256-Mbit Region # (KB) 128 111 6F0000 - 6FFFFF 6 128 96 600000 - 60FFFF 128 95 5F0000 - 5FFFFF 5 128 80 500000 - 50FFFF 128 79 ...
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P30 Family Table 8. Discrete Bottom Parameter Memory Maps (all packages) Programming Size Blk 256-Mbit Region (KB) 128 210 CF0000 - CFFFFF 12 128 195 C00000 - C0FFFF 128 194 BF0000 - BFFFFF 11 128 179 B00000 - B0FFFF ...
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Table 8. Discrete Bottom Parameter Memory Maps (all packages) Programming Size Blk 256-Mbit Region (KB) 128 18 0F0000 - 0FFFFF 128 4 010000 - 01FFFF 00C000 - 00FFFF 32 0 000000 - 03FFFF Table 9. 512-Mbit Memory ...
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P30 Family Table 10. 1-Gbit Memory Map (QUAD+ SCSP only) Flash Die # Die Stack Config. 4 (Top Parameter) 3 (Bottom Parameter) 2 (Top Parameter) 1 (Bottom Parameter) Note: Refer to 256-Mbit Memory Map April 2005 Intel StrataFlash 28 ...
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Maximum Ratings and Operating Conditions 5.1 Absolute Maximum Ratings Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Temperature under bias Storage temperature Voltage on any signal (except VCC, VPP) ...
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P30 Family 5.2 Operating Conditions Note: Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Table 11. Operating Conditions Symbol T Operating Temperature C V VCC Supply Voltage CC ...
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Electrical Specifications 6.1 DC Current Characteristics Table 12. DC Current Characteristics (Sheet Sym Parameter I Input Load Current LI Output I Leakage DQ[15:0], WAIT LO Current 64-Mbit 128-Mbit Standby, CCS CC 256-Mbit I ...
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P30 Family Table 12. DC Current Characteristics (Sheet Sym Parameter I V Program Current PPW Erase Current PPE PP Notes: 1. All currents are RMS unless noted. Typical values at typical V 2. ...
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AC Characteristics 7.1 AC Test Conditions Figure 13. AC Input/Output Reference Waveform V CCQ Input V 0V Note: AC test inputs are driven /2. Input rise and fall times (10% to 90%) < 5 ns. ...
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P30 Family 7.2 Capacitance Table 15. Capacitance Symbol Parameter Address, Data, CE#, WE#, OE#, C Input Capacitance IN RST#, CLK, ADV#, WP# C Output Capacitance Data, WAIT OUT NOTES: 1. Capacitance values are for a single die; for 2-die ...
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AC Read Specifications Table 16. AC Read Specifications for 64/128-Mbit Densities (Sheet Num Symbol Asynchronous Specifications R1 t Read cycle time AVAV t R2 Address to output valid AVQV t R3 CE# low to output valid ...
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P30 Family Table 16. AC Read Specifications for 64/128-Mbit Densities (Sheet Num Symbol R305 t Output hold from CLK CHQX R306 t Address hold from CLK CHAX R307 t CLK to WAIT valid CHTV R311 t ...
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Table 17. AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet Num Symbol R101 t Address setup to ADV# high AVVH R102 t CE# low to ADV# high ELVH R103 t ADV# low to output valid VLQV ...
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P30 Family Figure 16. Asynchronous Single-Word Read (ADV# Low) Address [A] ADV# CE# [E} OE# [G] R15 WAIT [ Data [D/Q] RST# [P] Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). Figure 17. ...
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Figure 18. Asynchronous Page-Mode Read Timing R2 A[Max:2] [A] A[1:0] R101 R105 R105 ADV# R3 CE# [E] R4 OE# [G] R15 WAIT [T] R7 DATA [D/Q] Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). Figure 19. ...
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P30 Family Figure 20. Continuous Burst Read, showing an Output Delay Timing R301 R302 R306 CLK [C] R2 R101 Address [A] R106 R105 R105 ADV# [V] R303 R102 R3 CE# [E] OE# [G] R15 WAIT [T] R7 Data [D/Q] ...
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Figure 21. Synchronous Burst-Mode Four-Word Read Timing R302 R301 R306 CLK [C] R2 R101 Address [A] A R105 R105 R106 R102 ADV# [V] R303 R3 CE# [E] OE# [G] R15 WAIT [T] R7 Data [D/Q] Note: WAIT is driven per ...
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P30 Family Table 18. AC Write Specifications (Sheet Num Symbol W14 t WE# high to OE# low WHGL W16 t WE# high to read valid WHQV Write to Asynchronous Read Specifications W18 t WE# high to ...
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Figure 23. Asynchronous Read-to-Write Timing R2 Address [A] R3 CE# [E} OE# [G] WE# [W] WAIT [ Data [D/Q] R5 RST# [P] Note: WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserted. ...
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P30 Family Figure 25. Synchronous Read-to-Write Timing R301 R302 R306 CLK [C] R2 R101 Address [A] R105 R105 R106 R102 ADV R303 R3 CE# [E] OE# [G] WE# WAIT [T] Data [D/Q] Note: WAIT shown deasserted and ...
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Program and Erase Characteristics Num Symbol Conventional Word Programming Program W200 t PROG/W Time Buffered Programming W200 t Program PROG/W Time W251 t BUFF Buffered Enhanced Factory Programming W451 t BEFP/W Program t BEFP/ W452 Setup Erasing and Suspending ...
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P30 Family 8.0 Power and Reset Specifications 8.1 Power Up and Down Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If VCCQ and/or VPP are not connected to the VCC supply, then V ...
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Figure 27. Reset Operation Waveforms (A) Reset during read mode (B) Reset during program or block erase P1 ≤ P2 (C) Reset during program or block erase P1 ≥ P2 (D) VCC Power-up to RST# high 8.3 Power Supply Decoupling ...
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P30 Family 9.0 Device Operations This section provides an overview of device operations. The system CPU provides control of all in- system read, write, and erase operations of the device via the system bus. The on-chip Write State Machine ...
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Writes To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted. During a write operation, address and data are latched on the rising edge of WE# or CE#, whichever occurs first. sequence ...
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P30 Family 9.2 Device Commands Device operations are initiated by writing specific device commands to the Command User Interface (CUI). See modify array data including Word Program and Block Erase commands. Writing either command to the CUI initiates a ...
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Table 20. Command Bus Cycles (Sheet Mode Command Program Protection Register Protection Program Lock Register Program Read Configuration Configuration Register Notes: 1. First command cycle address should be the same as the operation’s target address. DBA = ...
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P30 Family Table 21. Command Codes and Definitions (Sheet Mode Code Device Mode Alternate Word 0x10 Program Setup 0xE8 Buffered Program Buffered Program 0xD0 Confirm Write 0x80 BEFP Setup 0xD0 BEFP Confirm 0x20 Block Erase Setup ...
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Read Operations The device supports two read modes: asynchronous page mode and synchronous burst mode. Asynchronous page mode is the default read mode after device power- reset. The Read Configuration Register must be configured to enable synchronous ...
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P30 Family However, for a synchronous non-array read, the same word of data will be output on successive clock edges until the burst length requirements are satisfied. Refer to the following waveforms for more detailed information: • Figure 19, ...
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Table 22. Read Configuration Register Description (Sheet Burst Wrap (BW) 2:0 Burst Length (BL[2:0]) Note: Latency Code 2, Data Hold for a 2-clock data cycle ( WAIT must be deasserted with valid data (WD ...
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P30 Family Figure 28. First-Access Latency Count CLK [C] Valid Address [A] Address ADV# [V] Code 0 (Reserved) Valid DQ [D/Q] Output 15-0 Code 1 (Reserved DQ [D/Q] 15-0 Code 2 DQ [D/Q] 15-0 Code 3 DQ [D/Q] 15-0 ...
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Figure 29. Example Latency Count Setting using Code 3 CLK CE# ADV# A[MAX:0] D[15:0] 10.3.3 WAIT Polarity The WAIT Polarity bit (WP), RCR[10] determines the asserted level (V When WP is set, WAIT is asserted high (default). When WP is ...
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P30 Family Table 24. WAIT Functionality Table Condition CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’ CE# =’0’, OE# = ‘0’ Synchronous Array Reads Synchronous Non-Array Reads All Asynchronous Reads All Writes Notes: 1. ...
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WAIT Delay The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchronous burst reads. WAIT can be asserted either during or one data cycle before valid data is output on DQ[15:0]. When WD is set, WAIT is ...
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P30 Family boundary, the worst case output delay is one clock cycle less than the first access Latency Count. This delay can take place only once, and doesn’t occur if the burst sequence does not cross a device-row boundary. ...
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Programming Operations The device supports three programming methods: Word Programming (40h/10h), Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h, D0h). See 9.0, “Device Operations” on page 48 the device. The following sections describe device programming in detail. ...
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P30 Family During programming, the Write State Machine (WSM) executes a sequence of internally-timed events that program the desired data bits at the addressed location, and verifies that the bits are sufficiently programmed. Programming the flash memory array changes ...
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On the next write, a device start address is given along with the first data to be written to the flash memory array. Subsequent writes provide additional device addresses and data. All data addresses must lie within the start address ...
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P30 Family 11.3.1 BEFP Requirements and Considerations BEFP requirements: • Case temperature: T • V within specified operating range CC • VPP driven to V • Target block unlocked before issuing the BEFP Setup and Confirm commands • The ...
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Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. For BEFP, the count value for buffer loading is always the maximum buffer size of 32 words. During the buffer-loading ...
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P30 Family When a programming operation is executing, issuing the Program Suspend command requests the WSM to suspend the programming algorithm at predetermined points. The device continues to output Status Register data after the Program Suspend command is issued. ...
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Erase Operations Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. When a block is erased, all bits ...
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P30 Family To read data from the device (other than an erase-suspended block), the Read Array command must be issued. During Erase Suspend, a Program command can be issued to any block other than the erase-suspended block. Block erase ...
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Security Modes The device features security modes used to protect the information stored in the flash memory array. The following sections describe each security mode in detail. 13.1 Block Locking Individual instant block locking is used to protect user ...
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P30 Family down state, a Lock-Down command must be issued prior to changing WP blocks revert to the locked state upon reset or power up the device (see State Diagram” on page 13.1.4 Block Lock Status The ...
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SR[5 command sequence error occurs during an erase suspend, SR[4] and SR[5] remains set, even after the erase operation is resumed. Unless the Status Register is cleared using the Clear Status Register command before resuming the erase operation, ...
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P30 Family 13.3 Protection Registers The device contains 17 Protection Registers (PRs) that can be used to implement system security measures and/or device identification. Each Protection Register can be individually locked. The first 128-bit Protection Register is comprised of ...
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Figure 33. Protection Register Map 0x109 0x102 0x8A 13.3.1 Reading the Protection Registers The Protection Registers can be read from any address. To read the Protection Register, first issue the Read Device Identifier command at any address to place ...
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P30 Family The device programs the 64-bit and 128-bit user-programmable Protection Register data 16 bits at a time (see Figure 47, “Protection Register Programming Flowchart” on page Program Protection Register command outside of the Protection Register’s address space causes ...
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Special Read States The following sections describe non-array read states. Non-array reads can be performed in asynchronous read or synchronous burst mode. A non-array read operation occurs as asynchronous single-word mode. When non-array reads are performed in asynchronous page ...
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P30 Family Table 28. Status Register Description (Sheet Status Register (SR) 5 Erase Status (ES) 4 Program Status (PS Status (VPPS) PP Program Suspend Status 2 (PSS) Block-Locked Status 1 (BLS) 0 BEFP Status ...
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Table 29. Device Identifier Information Manufacturer Code Device ID Code Block Lock Configuration: • Block Is Unlocked • Block Is Locked • Block Is not Locked-Down • Block Is Locked-Down Configuration Register Lock Register 0 64-bit Factory-Programmed Protection Register 64-bit ...
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P30 Family Appendix A Write State Machine Figure 34 through Figure 39 incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read state (Read Array, Read Device ID, ...
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Figure 35. Write State Machine—Next State Table (Sheet Read Word Current Chip (2) (3,4) Array Program (7) State (FFH) (10H/40H) Setup Word Program Busy in Erase Suspend Busy Word Program in Erase Suspend Word Program Suspend in ...
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P30 Family Figure 36. Write State Machine—Next State Table (Sheet Command Input to Chip and resulting Chip Next State Lock OTP Block Current Chip (4) Setup (8) Confirm (7) State (C0H) (01H) OTP Ready Setup Ready ...
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Figure 37. Write State Machine—Next State Table (Sheet Command Input to Chip and resulting Chip Next State Lock Lock-Down OTP Block Current Chip (4) Setup (8) Confirm Confirm (7) State (C0H) (01H) Setup Word Program Busy in ...
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P30 Family Figure 38. Write State Machine—Next State Table (Sheet Output Next State Table Word Read Program (2) Array Current chip state Setup (3,4) (FFH) (10H/40H) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP ...
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Figure 39. Write State Machine—Next State Table (Sheet Output Next State Table Command Input to Chip and resulting Output Mux Next State Lock OTP Block (4) Setup (8) Current chip state Confirm (C0H) (01H) BEFP Setup, BEFP ...
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P30 Family 5. The Clear Status command only clears the error bits in the status register if the device is not in the following modes: WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP ...
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Appendix B Flowcharts Figure 40. Word Program Flowchart Start Write 0x40, (Setup) Word Address Write Data, (Confirm) Word Address Read Status Register 0 SR[ Full Status Check (if desired) Program Complete Read Status Register 1 SR[ ...
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P30 Family Figure 41. Program Suspend/Resume Flowchart Start Program Suspend Write B0h Any Address Read Status Write 70h Same Partition Read Status Register Read Array Write FFh Susp Partition Read Array ...
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Figure 42. Buffer Program Flowchart Supports Buffer Set Timeout or Loop Counter Get Next Target Address Issue Buffer Prog. Cmd. Word Address Read Status Register at Word Address Write Buffer Available? SR[7] = Write Word Count, Word Address Buffer Program ...
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P30 Family Figure 43. BEFP Flowchart BUFFERED ENHANCED FACTORY PROGRAMMING (BEFP) PROCEDURE Setup Phase Start V applied PP Block Unlocked Write 80h @ st 1 Word Address Write D0h @ st 1 Word Address BEFP Setup delay Read Status ...
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Figure 44. Block Erase Flowchart Start Write 0x20, (Block Erase) Block Address Write 0xD0, (Erase Confirm) Block Address Read Status Register 0 SR[ Full Erase Status Check (if desired) Block Erase Complete Read Status Register 1 SR[3] = ...
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P30 Family Figure 45. Erase Suspend/Resume Flowchart Start Write 0x70, Same Partition Write 0xB0, Any Address Read Status Register SR[7] = SR[6] = Read Read or Program? Read Array Data Done Write 0xD0, (Erase Resume) Any Address Erase Resumed ...
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Figure 46. Block Lock Operations Flowchart Start Write 0x60, Block Address Write either 0x01/0xD0/0x2F, Block Address Write 0x90 Read Block Lock Status Locking Change? Yes Write 0xFF Partition Address Lock Change Complete Datasheet Intel StrataFlash LOCKING OPERATIONS PROCEDURE Bus Command ...
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P30 Family Figure 47. Protection Register Programming Flowchart Start Write 0xC0, (Program Setup) PR Address Write PR (Confirm Data) Address & Data Read Status Register 0 SR[ Full Status Check (if desired) Program Complete Read Status Register ...
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Appendix C Common Flash Interface The Common Flash Interface (CFI) is part of an overall specification for multiple command-set and control-interface descriptions. This appendix describes the database structure containing the data returned by a read operation after issuing the CFI ...
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P30 Family Word Addressing: Offset Hex Code A – 00010h 0051 00011h 0052 00012h 0059 P_ID 00013h LO P_ID 00014h HI P 00015h LO P 00016h HI A_ID 00017h LO A_ID 00018h HI ... ... C.2 Query ...
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C.3 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s). Table 34. CFI Identification Offset Length 3 10h 2 13h ...
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P30 Family C.4 Device Geometry Definition Table 36. Device Geometry Definition Offset Length 27h 1 28h 2 2 2Ah 2Ch 1 4 2Dh 4 31h 4 35h A ddress 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: ...
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C.5 Intel-Specific Extended Query Table Table 37. Primary Vendor-Specific Extended Query (1) Offset Length P = 10Ah (P+0)h 3 Primary extended query table (P+1)h (P+2)h (P+3)h 1 Major version number, ASCII (P+4)h 1 Minor version number, ASCII (P+5)h 4 Optional ...
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P30 Family Table 38. Protection Register Information (1) Length Offset P = 10Ah (P+E)h 1 (P+F)h 4 (P+10)h (P+11)h (P+12)h (P+13)h 10 (P+14)h (P+15)h (P+16)h (P+17)h (P+18)h (P+19)h (P+1A)h (P+1B)h (P+1C)h Table 39. Burst Read Information (1) Length Offset ...
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Table 40. Partition and Erase-block Region Information (1) Offset P= 10Ah Bottom Top (P+23)h (P+23)h Number of device hardw are-partition regions w ithin the device. Datasheet Intel StrataFlash Description (Optional flash features and commands single hardw ...
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P30 Family Appendix D Additional Information Order/Document Number 290667 290737 290701 290702 252802 298161 253418 296514 297833 298136 300783 306667 306668 306669 Notes: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers ...
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Appendix E Ordering Information for Discrete Products Figure 48. Decoder for Discrete Intel StrataFlash T Package Designator TE = 56-Lead TSOP, leaded JS = 56-Lead TSOP, lead-free RC = 64-Ball Easy BGA, leaded PC = 64-Ball Easy BGA, lead-free Product ...
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... RD48F4000P0ZBQ0 RD48F4400P0VBQ0 RD48F4000P0ZTQ0 RD48F4400P0VTQ0 PF48F4000P0ZBQ0 PF48F4400P0VBQ0 PF48F4000P0ZTQ0 PF48F4400P0VTQ0 RC48F4400P0VB00 RC48F4400P0VT00 PC48F4400P0VB00 PC48F4400P0VT00 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Q 0 Device Details 0 = Original version of the product (refer to the latest version of the datasheet for details) Ballout Designator Q = QUAD ballout ...