mpc961p Integrated Device Technology, mpc961p Datasheet

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mpc961p

Manufacturer Part Number
mpc961p
Description
Lvpecl-input Lvcmos-ouput 200-mhz Low Voltage Clock Zero Delay Buffer
Manufacturer
Integrated Device Technology
Datasheet

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IDT™ Low Voltage Zero Delay Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
Low Voltage Zero Delay Buffer
Freescale Semiconductor, Inc.
TECHNICAL DATA
Low Voltage Zero Delay Buffer
buffer. With output frequencies of up to 200 MHz, output skews of 150 ps the
device meets the needs of the most demanding clock tree applications.
Features
Functional Description
MPC961P offers an LVCMOS reference clock while the MPC961P offers an
LVPECL reference clock.
affect the QFB output, down stream clocks can be disabled without the internal PLL losing lock.
compatible levels and the outputs provide low impedance LVCMOS outputs capable of driving terminated 50 Ω transmission lines.
For series terminated lines the MPC961 can drive two lines per output giving the device an effective fanout of 1:36. The device is
packaged in a 32 lead LQFP package to provide the optimum combination of board density and performance.
492
The MPC961 is a 2.5 V or 3.3 V compatible, 1:18 PLL based zero delay
The MPC961 is offered with two different input configurations. The
When pulled high the OE pin will force all of the outputs (except QFB) into a high impedance state. Because the OE pin does not
The MPC961 is fully 2.5 V or 3.3 V compatible and requires no external loop filter components. All control inputs accept LVCMOS
Up to 200 MHz I/O Frequency
LVCMOS Outputs
Outputs Disable in High Impedance
LVPECL Reference Clock Options
LQFP Packaging
32-lead Pb-free Package Available
±50 ps Cycle-Cycle Jitter
150 ps Output Skews
Fully Integrated PLL
The MPC961P requires an external RC filter for the analog power supply pin V
F_RANGE
FB_IN
PCLK
PCLK
OE
50 k
50 k
50 k
50 k
V
CC
50 k
50 k
Figure 1. MPC961P Logic Diagram
Ref
FB
100 – 200 MHz
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
50 – 100 MHz
PLL
1
CCA
. Refer to
0
1
APPLICATIONS INFORMATION
ZERO DELAY BUFFER
32-LEAD LQFP PACKAGE
MPC961P
LOW VOLTAGE
CASE 873A-03
FA SUFFIX
Q0
Q1
Q2
Q3
Q14
Q15
Q16
QFB
Order number: MPC961P
for details.
DATA SHEET
Rev 3, 08/2004
MPC961P
MPC961P

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mpc961p Summary of contents

Page 1

... LQFP package to provide the optimum combination of board density and performance. PCLK PCLK FB_IN F_RANGE OE The MPC961P requires an external RC filter for the analog power supply pin V 492 IDT™ Low Voltage Zero Delay Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc V CC ...

Page 2

... Clock outputs LVCMOS PLL feedback signal output, connect to a FB_IN Ground Negative power supply V PLL positive power supply (analog power supply). The MPC961P requires an CC external RC filter for the analog power supply pin V section for details. V Positive power supply for I/O and core ...

Page 3

... CMR PP 2. The MPC961P is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission . Alternatively, the device drives up two 50 Ω series terminated transmission lines. line to a termination voltage Table 5. AC Characteristics (V ...

Page 4

... Exceeding the specified V /V CMR PP 2. The MPC961P is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission . Alternatively, the device drives up two 50 Ω series terminated transmission lines. line to a termination voltage Table 7. AC Characteristics (V ...

Page 5

... V DC current and thus only a single terminated line can be driven by each output of the MPC961P clock driver. For the series terminated case however there current draw, thus the outputs can drive multiple series terminated lines. ...

Page 6

... Calculation of Part-to-Part Skew The MPC961P zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC961P are connected together, the maximum overall timing uncertainty from the common PCLK input to any output is: ...

Page 7

... Power Consumption of the MPC961P and Thermal Management The MPC961P AC specification is guaranteed for the entire operating frequency range up to 200 MHz. The MPC961P power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board ...

Page 8

... According to Table 9.Die Junction Temperature and junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the MPC961P in a series terminated transmission line system. Table 10. Thermal Package Impedance of the 32ld LQFP R ...

Page 9

... FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 3 2.4 0. Figure 13. Output Transition Time Test Reference t SK(O) Figure 15. Output-to-Output Skew t SK( –1/f JIT(PER Figure 17. Period Jitter NETCOM 1 ÷ GND V CC ÷ GND | 0 MPC961P ...

Page 10

... MPC961P PART NUMBERS Low Voltage Zero Delay Buffer INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road ...

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