mpc96877 Integrated Device Technology, mpc96877 Datasheet

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mpc96877

Manufacturer Part Number
mpc96877
Description
1.8 V Pll 1 10 Differential Sdram Clock Driver
Manufacturer
Integrated Device Technology
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
mpc96877VK
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT™ 1.8 V PLL 1:10 Differential SDRAM Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
1.8 V PLL 1:10 Differential SDRAM
Clock Driver
Freescale Semiconductor, Inc.
TECHNICAL DATA
Product Preview
1.8 V PLL 1:10 Differential SDRAM
Recommended Applications
Features
Switching Characteristics
Functional Description
that distributes a differential clock input pair (CK, CK) to ten differential pairs of
clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs
(FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK,
CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS),
and the analog power input (AV
FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin
that must be tied to GND or V
no affect on Y7/Y7, they are free running. When AV
clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs,
independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the
PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and
the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK,
CK) within the specified stabilization time.
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
The MPC96877 is a high-performance, low-jitter, low-skew, zero-delay buffer
The MPC96877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from 0°C to 70°C.
DDR II Memory Modules
Zero Delay Board fan-out
1.8 V Phase Lock Loop Clock Driver for (DDR II) Applications
Spread Spectrum Clock Compatible
Operating Frequency: 100 MHz to 340 MHz
1 to 10 differential clock distribution (SSTL_18)
52-Ball VF-BGA (FP-MAPBGA 0.65-mm pitch) and 40-Pin MLF (QFN)
52-lead Pb-free Package Available
External Feedback Pins (FBIN, FBIN) are used to synchronize the Outputs
to the Input Clocks
Single-Ended Input and Single-Ended Output Modes
Meets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300
Auto Power Down detect logic
Cycle-to-Cycle Jitter (>165 Mhz): 40 ps max.
Output-to-Output Skew: 40 ps max.
DD
DD
. When OS is high, OE functions as previously described. When OS and OE are both low, OE has
). When OE is low, the clock outputs, except
DD
is grounded, the PLL is turned off and bypassed for test purposes. When both
1
0
°
C to 70
T
AVAILABLE ORDERING OPTIONS
CLOCK / ZERO DELAY BUFFER
A
52-BALL FP-MAPBGA PACKAGE
°
40-PIN MLF/QFN PACKAGE
C
MPC96877
DDR II MEMORY
MPC96877VK
CASE 1544-01
CASE 1545-01
52-Ball BGA
VK SUFFIX
EP SUFFIX
(Pb-Free)
Order number: MPC96877
DATA SHEET
MPC96877
MPC96877EP
40-Pin QFN
Rev 1, 08/2004
(Pb-Free)
MPC96877
547

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mpc96877 Summary of contents

Page 1

... PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time. The MPC96877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from 0°C to 70°C. FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA IDT™ ...

Page 2

... IDT™ 1.8 V PLL 1:10 Differential SDRAM Clock Driver 548 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc LD Powerdown LD Control and Test Logic PLL bypass LD * PLL Figure 1. MPC96877 Logic Diagram FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 2 NETCOM ...

Page 3

... Pitch, M0#220, Variation VJJD- 2.9 mm ±0.15 mm) Package Pinouts 3 NETCOM MPC96877 EP PACKAGE (TOP VIEW DDQ 4 27 FBIN 5 26 FBIN GND 6 FBOUT FBOUT DDQ MPC96877 549 ...

Page 4

... limit in Table 5. ODL FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 4 NETCOM Function ) DD PLL FBOUT FBOUT L H Bypassed / OFF H L Bypassed / OFF L H Bypassed / OFF H L Bypassed / OFF OFF RESERVED MPC96877 ...

Page 5

... Min Nom Max 1.7 1.8 1.9 V DDQ 0. DDQ 0. DDQ – /2) –0.15 (V /2) +0.15 DDQ DDQ –0.3 V +0.3 DDQ 0.3 V +0.4 DDQ 0.6 V +0.4 DDQ 0 70 remains within the recommended DDQ Figure 12. Time Delay between OE and Clock NETCOM + 0 0.5 V Unit ° C MPC96877 551 ...

Page 6

... V 0.5 or GND 1.9 V ± 250 or GND 1.9 V ± 10 1.9 V 500 1.9 V 300 ) where F is the input Frequency the power CK DDQ 1.8 V ± 0 DDQ Min Max 125 340 160 340 NETCOM Unit µA V µA µA mA Unit MHz MHz % µs MPC96877 ...

Page 7

... Figure 4. Output Load Test Circuit 7 NETCOM MPC96877 V = 1.8 V ± 0.1 V DD, DDQ Unit Nom Max – V/ns 2.5 4 2.5 3 V/ns (V /2) + 0.1 V DDQ 33 kHz –0.5 MHz is used to measure is used to measure all other tests measured single ended. MPC96877 553 ...

Page 8

... Figure 3. Output Load Test Circuit 1 C=10pF -V DDQ /2 Z=60 Ω Z=50 Ω R=10 Ω L=2.97" Z=60 Ω Z=50 Ω R=10 Ω L=2.97" C=10pF -V DDQ /2 Figure 4. Output Load Test Circuit 2 FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 8 NETCOM SCOPE R=1MΩ C=1pF R=1MΩ C=1pF SCOPE R=1MΩ R=1MΩ Note GND MPC96877 ...

Page 9

... Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc t cycle n t jit(cc cycle cycle n+1 Figure 5. Cycle-to-Cycle Period Jitter t (ø) n n=N ∑ t (ø (ø Figure 6. Static Phase Offset sk(0) Figure 7. Output Skew 9 MPC96877 t cycle n+1 t (ø) n large number of samples) NETCOM MPC96877 555 ...

Page 10

... Figure 8. Period Jitter jit(hper cycle Figure 9. Half-Period Jitter 80% 20 r( f( 20% slrr (i/o) = slrf (i/ r(i/o) Figure 10. Input and Output Slew Rates FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA 10 NETCOM t half period n any half cycle 80% 20 20% t f(i/o) MPC96877 ...

Page 11

... SSC OFF SSC ON t (ø) dyn t (ø) dyn Figure 11. Dynamic Phase Offset 50% V DDQ t en 50% V DDQ 50% V DDQ Figure 12. Time Delay between OE and Clock Output 11 MPC96877 t (ø) SSC OFF SSC ON t (ø) dyn 50% V DDQ t dis NETCOM MPC96877 557 ...

Page 12

... PLL and caps to AGND to AGND trace & connect trace to one GND via (farthest from PLL). 3. Recommended bead: Fair Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz) Figure 13. AV Filtering DD FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA VDD 4.7 uF 4.7 uF PLL 1206 1206 AGND NETCOM MPC96877 ...

Page 13

... MPC96877 PART NUMBERS 1.8 V PLL 1:10 Differential SDRAM Clock Driver INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road ...

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