Manufacturer Part Numbermpc970
DescriptionLow Voltage Pll Clock Driver
ManufacturerFreescale Semiconductor, Inc
mpc970 datasheet

Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
Page 9
Page 10
Page 1/16

Download datasheet (150Kb)Embed
Not Recommended for New Designs
See MPC972 or MPC974
Low Voltage PLL Clock Driver
The MPC970 is a 3.3V compatible, PLL based clock driver devices
targeted for high performance RISC or CISC processor based systems.
Fully Integrated PLL
Output Frequency Up to 250MHz
Compatible with PowerPC
and Pentium
Output Frequency Configuration
On–Board Crystal Oscillator
52–Lead TQFP Packaging
50ps Typical Cycle–to–Cycle Jitter
The MPC970 was designed specifically to drive today’s PowerPC 601
and Pentium processors while providing the necessary performance to
address higher frequency PowerPC 601 as well as PowerPC 603 and
PowerPC 604 applications. The 2x_PCLK output can toggle at up to
250MHz while the remaining outputs can be configured to drive the other
system clocks for MPC 601 based systems. As the processor based
clock speeds increase the processor bus will likely run at one third or
even one fourth the processor clock. The MPC970 supports the
necessary waveforms to drive the BCLKEN input signal of the MPC 601
when the processor bus is running at a lower frequency than the
processor. The MPC970 uses an advanced PLL design which minimizes
the jitter generated on the outputs. The jitter specification is well within the
requirements of the Pentium processor and meets the stringent
preliminary specifications of the PowerPC 603 and PowerPC 604
processors. The application section of this data sheet deals in more detail
with driving PowerPC and Pentium processor based systems.
The external feedback option of the MPC970 provides for a near zero delay between the reference clock input and the outputs
of the device. This feature is required in applications where a master clock is being picked up off the backplane and regenerated
and distributed on a daughter card. The advanced PLL of the MPC970 eliminates the dead zone of the phase detector and
minimizes the jitter of the PLL so that the phase error variation is held to a minimum. This phase error uncertainty makes up a
major portion of the part–to–part skew of the device.
For single clock driver applications the MPC970 provides an internal oscillator and internal feedback to simplify board layout
and minimize system cost. By using the on–board crystal oscillator the MPC970 acts as both the clock generator and distribution
chip. The external component is a relatively inexpensive crystal rather than a more expensive oscillator. Since in single board
applications the delay between the input reference and the outputs is inconsequential an internal feedback option is offered. The
internal feedback simplifies board design in that the system designer need not worry about noise being coupled into the feedback
line due to board parasitics and layout. The internal feedback is a fixed divide by 32 of the VCO. This divide ratio ensures that the
input crystals will be 20MHz, thus keeping the crystal costs down and ensuring availability from multiple vendors.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
Motorola, Inc. 1997
CASE 848D–03

mpc970 Summary of contents

  • Page 1

    ... This feature is required in applications where a master clock is being picked up off the backplane and regenerated and distributed on a daughter card. The advanced PLL of the MPC970 eliminates the dead zone of the phase detector and minimizes the jitter of the PLL so that the phase error variation is held to a minimum. This phase error uncertainty makes up a major portion of the part– ...

  • Page 2

    ... The MPC970 allows for the enabling of each output independently via a serial input port or a common enable/disable of all outputs simultaneously via a parallel control pin. When disabled or “frozen” the outputs will be locked in the “LOW” state, however the internal state machines will continue to run. Therefore when “ ...

  • Page 3

    ... Serial Freeze Mux Input bclk4_frz Register Register pci_clk0_frz pci_clk1_frz pci_clk2_frz pci_clk3_frz pci_clk4_frz pci_clk5_frz pci_clk6_frz Figure 2. Simplified Block Diagram 3 MPC970 Freeze, 2x_PCLK De–Skew PCLKEN Freeze, De–Skew Freeze, BCLKEN De–Skew Freeze, BCLK0 De–Skew BCLK1 Freeze, De–Skew BCLK2 Freeze, De–Skew Freeze, BCLK3 De– ...

  • Page 4

    ... Output is purposely delayed vs 2x_PCLK output. FUNCTION TABLE 2 PCI_Div1 PCI_Div0 FUNCTION TABLE 3 Control Pin MOTOROLA MPC970 Figure 3. 52–Lead Pinout (Top VIew) PCLKEN BCLKEN VCO/4 VCO/4 VCO/4 BCLK* PCI_CLK BCLK_Div1 BLCK 0 BCLK/2 0 BCLK/3 ...

  • Page 5

    ... Input Capacitance C pd Power Dissipation Capacitance C OUT Output Capacitance 1. The MPC970 outputs can drive series or parallel terminated 50Ω (or 50Ω /2) transmission lines on the incident edge (see Applications Info section). PLL INPUT REFERENCE CHARACTERISTICS ( Symbol Characteristic ...

  • Page 6

    ... MPC970 AC CHARACTERISTICS ( Symbol Characteristic f Xtal Crystal Oscillator Frequency F out Maximum 2x_PCLK Output Frequency t DC Output Duty Cycle (Notes 4., 5 Output HIGH Voltage Output LOW Voltage t pw 2x_PCLK Pulse Width (Notes 4., 5.) t per Minimum Clock Out Period ...

  • Page 7

    ... The PLL_En pin allows the TClk input to be routed around the PLL for system test and debug. When pulled low the MPC970 will be placed in the test mode. Note that the TClk input will be routed through the divider chain. For instance in the PowerPC 601 microprocessor clock generation mode the TClk input will toggle twice for each toggle on the 2x_PCLK output ...

  • Page 8

    ... BCLKEN input of the MPC 601 the BCLKEN output of the MPC970 lags the 2xPCLK output by no less than 100ps. When the MPC970 is not in the MPC601_Clks mode the BCLKEN output is set at a fixed divide by four from the internal VCO. In addition in this mode the BCLKEN output does NOT lag the other outputs, but rather is synchronous within the Output– ...

  • Page 9

    ... BCLK_En output is delayed relative to other outputs TIMING SOLUTIONS BR1333 — Rev 6 the feedback output. If, for instance the MPC970 used as a zero delay buffer the VCO_Sel pin should be pulled LOW and all of the outputs should be set in a VCO/4 mode. This would produce a feedback ratio of 8. Several potential configurations using the external feedback are pictured in Figure 4 through Figure 7 ...

  • Page 10

    ... VCO/8 VCO/4 VCO/4 VCO/12 VCO/4 VCO/4 VCO/16 VCO/4 MPC970 2x_PCLK (VCO/4) PCLKEN (VCO/4) BCLKEN (VCO/4) BCLK0:4 (VCO/4) PCI_CLK0:6 (VCO/8) 400 VCO 1000 MPC970 2x_PCLK (VCO/4) PCLKEN (VCO/4) BCLKEN (VCO/4) BCLK0:4 (VCO/8) PCI_CLK0:6 (VCO/16) 400 VCO 1000 TIMING SOLUTIONS BR1333 — Rev 6 ...

  • Page 11

    ... BR1333 — Rev 6 produce the desired output frequency for an application which utilizes internal feedback the block diagram of Figure 8 should be used. The P and the M values for the MPC970 are also included in Figure 8. The M values can be found in the configuration tables included in this applications section. ...

  • Page 12

    ... VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC970 clock driver. For the series terminated case however there current draw, thus the outputs can drive multiple series terminated lines. ...

  • Page 13

    ... The period of each Frz_Data bit equals the period of the free–running Frz_Clk signal. The Frz_Data serial transmission should be timed so the MPC970 can sample each Frz_Data bit with the rising edge of the free–running Frz_Clk signal. Start ...

  • Page 14

    ... A typical system for these processors will include 8 – 16 clock loads on the processor bus. When the MPC970 is taken out of the MPC601_Clk mode there are a total of 8 “non PCI_CLK” outputs which can be run at the processor bus speeds for these microprocessors. Since ...

  • Page 15

    ... 0.10 (0.004) T VIEW θ1 0.25 (0.010) θ GAGE PLANE MPC970 –X– X= VIEW Y BASE METAL F PLATING Ç Ç Ç Ç É É É É É É É É Ç Ç Ç Ç D 0.13 (0.005) T L– ...

  • Page 16

    ... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 16 MPC970/D TIMING SOLUTIONS BR1333 — Rev 6 ...