mpc970 Freescale Semiconductor, Inc, mpc970 Datasheet - Page 12

• Manufacturer Part Number: mpc970
• Description: Low Voltage Pll Clock Driver
• Manufacturer: Freescale Semiconductor, Inc

MPC970
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC970 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 9 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC970 clock
driver is effectively doubled due to its capability to drive
multiple lines.
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC970 output buffers is
more than sufficient to drive 50Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC970. The output waveform
in Figure 10 shows a step in the waveform, this step is
caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 43Ω series resistor
plus the output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
unity reflection coefficient, to 2.8V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 11 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
MOTOROLA
IN
IN
The waveform plots of Figure 10 show the simulation
At the load end the voltage will double, due to the near
Since this step is well above the threshold region it will not
Figure 9. Single versus Dual Transmission Lines
VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
OUTPUT
OUTPUT
BUFFER
MPC970
BUFFER
MPC970
7Ω
7Ω
R S = 43Ω
R S = 43Ω
R S = 43Ω
Z O = 50Ω
Z O = 50Ω
Z O = 50Ω
OutA
OutB0
OutB1
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engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
Using the Output Freeze Circuitry
computers the desire for unique power management among
system designers is keen. The individual output enable
control of the MPC970 allows designers, under software
control, to implement unique power management schemes
into their designs. Although useful, individual output control
at the expense of one pin per output is too high, therefore a
simple serial interface was derived to economize on the
control pins.
which the MPC970 clock outputs may be frozen (stopped in
the logic ‘0’ state):
13–bit Serial Input Register, this register contains one
programmable freeze enable bit for 13 of the 15 output
clocks. The BCLK0 and PCI_CLK0 outputs cannot be frozen
with the serial port, this avoids any potential lock up situation
SPICE level output buffer models are available for
With the recent advent of a “green” classification for
The freeze control logic provides two mechanisms through
The first freeze mechanism allows serial loading of the
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 11. Optimized Dual Line Termination
Figure 10. Single versus Dual Waveforms
OUTPUT
MPC970
BUFFER
7Ω
t D = 3.8956
2
In
OutA
7Ω + 36Ω
4
R S = 36Ω
R S = 36Ω
25Ω = 25Ω
k
6
36Ω = 50Ω
TIME (nS)
t D = 3.9386
OutB
8
Z O = 50Ω
Z O = 50Ω
k
TIMING SOLUTIONS
50Ω
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BR1333 — Rev 6
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