mpc970 Freescale Semiconductor, Inc, mpc970 Datasheet - Page 2

• Manufacturer Part Number: mpc970
• Description: Low Voltage Pll Clock Driver
• Manufacturer: Freescale Semiconductor, Inc

MPC970
as well as provide unique opportunities for system power down schemes to meet the requirements of “green” class machines.
The MPC970 allows for the enabling of each output independently via a serial input port or a common enable/disable of all
outputs simultaneously via a parallel control pin. When disabled or “frozen” the outputs will be locked in the “LOW” state, however
the internal state machines will continue to run. Therefore when “unfrozen” the outputs will activate synchronous and in phase
with those outputs which were not frozen. The freezing and unfreezing of outputs occurs only when they are already in the “LOW”
state, thus the possibility of runt pulse generation is eliminated. A power–on reset will ensure that upon power up all of the outputs
will be active.
flops will be reset. In addition the internal PLL can be bypassed and the fanout dividers and output buffers can be driven directly
by the TClk input pin. Note that in this mode it will take a number of input clock pulses to cause output transitions as the TClk is
fed through the internal dividers.
inputs accept LVCMOS/LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive 50Ω
transmission lines. For series terminated lines each MPC970 output can drive two 50Ω lines in parallel thus effectively doubling
the fanout of the device.
MOTOROLA
The MPC970 offers a very flexible output enable/disable scheme. This enable/disable scheme helps facilitate system debug
For IC and board level testing a MR/Tristate input is provided. When pulled “LOW” all outputs will tristate and all internal flip
The MPC970 is fully 3.3V (3.6V for PowerPC 601 designs) compatible and requires no external loop filter components. All
MPC601_CLKs
MR/Tristate
Frz_Strobe
BClk_Div0
BClk_Div1
IntFB_Sel
PCI_Div0
PCI_Div1
VCO_Sel
Frz_Data
Com_Frz
Ref_Sel
PLL_En
Frz_Clk
Ext_FB
xtal1
xtal2
TClk
Figure 1. Enable/Disable Scheme
Dividers
Register
Control
Freeze
Clock
PLL
2
De–Skew,
3–State
Freeze
Drivers
Clock,
2x_PCLK
PCLKEN
BCLKEN
BCLK0
BCLK1
BCLK2
BCLK3
BCLK4
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
PCI_CLK6
TIMING SOLUTIONS
BR1333 — Rev 6