mpc970 Freescale Semiconductor, Inc, mpc970 Datasheet - Page 7

• Manufacturer Part Number: mpc970
• Description: Low Voltage Pll Clock Driver
• Manufacturer: Freescale Semiconductor, Inc

of the MPC970 I/O. Unless explicitly stated all inputs are
LVCMOS/LVTTL compatible with internal pull up resistors. All
outputs are LVCMOS level outputs which are capable of
driving two series terminated 50Ω transmission lines on the
incident edge.
xtal1, xtal2
external crystal connections to the internal oscillator. The
crystal oscillator is completely self contained, there are no
external components required. The oscillator is specified to
function for crystals of up to 50MHz. Exact crystal
specifications are outlined in the applications section.
VCO_Sel
internal VCO frequency for the generation of lower
frequencies at the outputs. The VCO_Sel pin should be used
to set the VCO into its most optimum range. Refer to the
applications section for more details on the VCO frequency
range. A logic ‘1’ on the VCO_Sel pin will bypass the internal
TClk
either a reference clock input for the PLL from an external
frequency source or it can be used as a board level test clock
in the PLL bypass mode.
PLL_En
the PLL for system test and debug. When pulled low the
MPC970 will be placed in the test mode. Note that the TClk
input will be routed through the divider chain. For instance in
the PowerPC 601 microprocessor clock generation mode the
TClk input will toggle twice for each toggle on the 2x_PCLK
output. Depending on the states of the frequency divider
select pins this ratio may be higher.
Frz_Data
function of the device. Refer to the applications section for
more information on the freeze functionality.
Frz_Clk
applications section for more information on the freeze
functionality.
Frz_Strobe
the outputs simultaneously. Refer to the applications section
for more information on the freeze functionality.
TIMING SOLUTIONS
BR1333 — Rev 6
2.
The following gives a brief description of the functionality
For the MPC970 the xtal1 and xtal2 pins represent the
The VCO_Sel pin allows the user to further divide the
The TClk input serves a dual purpose; it can be used as
The PLL_En pin allows the TClk input to be routed around
Frz_Data is the serial data input for the output freeze
Frz_Clk is the serial freeze logic clock input. Refer to the
The Frz_Strobe input is used to freeze or unfreeze all of
DETAILED PIN DESCRIPTIONS
7
Com_Frz
the outputs with the control of a single pin. The action will
take place upon a high to low transition of the Frz_Strobe
input.
BClk_Div0:1
ratio for the BCLK outputs. These inputs also set the divide
ratio of the BCLKEN output to be equal in frequency to the
BCLK outputs when the device is in the MPC601_Clks mode.
The BClk_Div inputs set the frequency as follows:
In most applications these inputs will be strapped to the
appropriate power rails.
PCI_Div0:1
PCI_CLKs. The PCI_CLKs are set relative to the BCLK or the
PCLKEN output such that you can upgrade the processor
bus and maintain the PCI bus frequency in the currently
defined
PCI_CLKs as follows:
In a typical application these inputs will be strapped to the
appropriate power rail.
MPC601_Clks
the PowerPC 601 microprocessor when pulled HIGH or left
open. When pulled LOW it will configure the 2xPCLK,
PCLKEN and BCLKEN all into a VCO/4 mode. In this mode
the MPC970 will have three more outputs available to drive
clock loads on the processor bus for PowerPC 603,
PowerPC 604 or Pentium microprocessor based systems.
Ext_FB
which is tied to an external feedback output. Typically this
feedback will be one of the lowest frequency outputs of the
MPC970.
IntFB_Sel
signal or an external feedback signal is routed to the phase
detector of the PLL. The default mode, pulled HIGH via the
internal pull up resistor, is to select the internal feedback.
The Com_Frz input allows the user to enable/disable all of
The BClk_Div inputs are used to program the VCO divide
The PCI_Div inputs set the division ratio for the
The MPC601_Clks input will configure the outputs to drive
The Ext_FB pin is an input to the phase detector of the PLL
The IntFB_Sel input selects whether the internal feedback
PCI_Div1
BClk_Div1
0
0
1
1
0
0
1
1
33MHz range. The PCI_Div inputs set the
PCI_Div0
BClk_Div0
0
1
0
1
0
1
0
1
PCI_CLK Frequency
BCLK Frequency
PCLKEN
BCLK/2
BCLK/3
PCLKEN/2
PCLKEN/3
PCLKEN/4
BCLK
PCLKEN
MPC970
MOTOROLA