mpc9952 Freescale Semiconductor, Inc, mpc9952 Datasheet

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mpc9952

Manufacturer Part Number
mpc9952
Description
Low Voltage Pll Clock Driver
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Low Voltage PLL Clock Driver
targeted for high performance clock tree applications. The device
features a fully integrated PLL with no external components required.
With output frequencies of up to 180MHz and eleven low skew outputs
the MPC9952 is well suited for high performance designs. The device
employs a fully differential PLL design to optimize jitter and noise
rejection performance. Jitter is an increasingly important parameter as
more microprocessors and ASiC’s are employing on chip PLL clock
distribution.
outputs. The banks contain 5 outputs, 4 outputs and 2 outputs. The
internal divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1
and 3:2:1. The output frequency relationship is controlled by the fsel
frequency control pins. The fsel pins as well as the other inputs are
LVCMOS/LVTTL compatible inputs.
for the use of the device as a “zero delay” buffer. Any of the eleven
outputs can be used as the feedback to the PLL. The VCO_Sel pin allows for the choice of two VCO ranges to optimize PLL
stability and jitter performance. The MR/OE pin allows the user to force the outputs into high impedance for board level test.
signal on the RefClk input around the PLL directly to the internal dividers. Because the signal is routed through the dividers, it
may take several transitions of the RefClk to affect a transition on the outputs. This features allows a designer to single step the
design for debug purposes.
For applications using series terminated transmission lines each MPC9952 output can drive two lines. This capability provides an
effective fanout of 22, more than enough clocks for most clock tree designs. For more information on driving transmission lines
consult the applications section of this data sheet.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
03/01
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 2001
Fully Integrated PLL
Output Frequency up to 180MHz
High Impedance Disabled Outputs
Compatible with PowerPC , Intel and High Performance RISC
Microprocessors
Output Frequency Configurable
LQFP Packaging
The MPC9952 is a 3.3V compatible, PLL based clock driver device
The MPC9952 features three banks of individually configurable
The MPC9952 uses external feedback to the PLL. This features allows
For system debug the PLL of the MPC9952 can be bypassed. When forced to a logic HIGH, the PLLEN input will route the
The outputs of the MPC9952 are LVCMOS outputs. The outputs are optimally designed to drive terminated transmission lines.
100ps Cycle–to–Cycle Jitter
1
REV 2
PLL CLOCK DRIVER
MPC9952
LOW VOLTAGE
LQFP PACKAGE
CASE 873A-02
FA SUFFIX
Order this document
by MPC9952/D

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mpc9952 Summary of contents

Page 1

... The MR/OE pin allows the user to force the outputs into high impedance for board level test. For system debug the PLL of the MPC9952 can be bypassed. When forced to a logic HIGH, the PLLEN input will route the signal on the RefClk input around the PLL directly to the internal dividers. Because the signal is routed through the dividers, it may take several transitions of the RefClk to affect a transition on the outputs ...

Page 2

... VCCO 25 Qb2 26 Qb3 27 GNDO 28 MPC9952 GNDO 29 Qc0 30 Qc1 31 VCCO Figure 2. 32–Lead Pinout (Top View) MOTOROLA Figure 1. MPC9952 Logic Diagram VCO 2 200–480MHz LPF FUNCTION TABLES fsela VCCO 15 Qa2 Control Pin 14 Qa1 VCO_Sel 13 GNDO MR/OE 12 Qa0 PLL_En ...

Page 3

... Maximum Quiescent Supply Current I CCA PLL Supply Current 1. The MPC9952 outputs can drive series or parallel terminated 50 ( CCO /2) transmission lines on the incident edge (see Applications Info section). 2. Inputs have pull–up, pull–down resistors which affect input current. PLL INPUT REFERENCE CHARACTERISTICS ( ...

Page 4

... Figure 3 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9952 clock driver is effectively doubled due to its capability to drive multiple lines. ...

Page 5

... DC voltage drop that will be seen between the V CC supply and the VCCA pin of the MPC9952. From the data sheet the I VCCA current (the current sourced through the VCCA pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.3V – 5% must be maintained on the VCCA pin very little DC voltage drop can be tolerated when a 3 ...

Page 6

... MPC9952 –T– DETAIL –Z– –AB– SEATING –AC– PLANE 0.10 (0.004 DETAIL AD MOTOROLA OUTLINE DIMENSIONS FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A 4X 0.20 (0.008) AB T–U Z –U– ...

Page 7

... TIMING SOLUTIONS DL207 — Rev 0 NOTES 7 MPC9952 MOTOROLA ...

Page 8

... JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 8 TIMING SOLUTIONS MPC9952/D DL207 — Rev 0 ...

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