mpc904 Freescale Semiconductor, Inc, mpc904 Datasheet - Page 4

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mpc904

Manufacturer Part Number
mpc904
Description
Mpc903 1 6 Pci Clock Generator/ Fanout Buffer
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC904
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
MPC903 MPC904 MPC905
Driving Transmission Lines
high speed signals in a terminated transmission line
environment. To provide the optimum flexibility to the user the
output drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 10Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC903/904/905 clock
driver. For the series terminated case however there is no DC
current draw, thus the outputs can drive multiple series
terminated lines. Figure 4 illustrates an output driving a
single series terminated line vs two series terminated lines in
parallel. When taken to its extreme the fanout of the
MPC903/904/905 clock driver is effectively doubled due to its
capability to drive multiple lines.
MOTOROLA
The MPC903/904/905 clock driver was designed to drive
In most high performance clock networks point–to–point
ENABLE2
ENABLE1
BCLK0–4
BCLK5
APPLICATIONS INFORMATION
Figure 3. Enable Timing Diagram
4
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC903/904/905 output
buffers is more than sufficient to drive 50Ω transmission lines
on the incident edge. Note from the delay measurements in
the simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
IN
IN
The waveform plots of Figure 5 show the simulation
Figure 4. Single versus Dual Transmission Lines
OUTPUT
OUTPUT
MPC903
BUFFER
MPC903
BUFFER
7Ω
7Ω
R S = 43Ω
R S = 43Ω
R S = 43Ω
Z O = 50Ω
Z O = 50Ω
Z O = 50Ω
TIMING SOLUTIONS
BR1333 — REV 5
OutA
OutB0
OutB1

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