mc88915 Integrated Device Technology, mc88915 Datasheet
mc88915
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mc88915 Summary of contents
Page 1
... PC's and workstations. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it to multiple components on a board. The PLL also allows the MC88915 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency ...
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... Input Asynchronous reset (active low) Input Disables phase-lock for low frequency testing Power and ground pins (note pins 8 and 10 are “quiet” supply pins for internal logic only Q/2 24 GND GND 19 LOCK Function MC88915 REV 6 JULY 10, 2007 ...
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... MUX (÷ (÷ DIVIDE BY TWO FREQ_SEL Figure 2. MC88915 Block Diagram 3 LOCK VOLTAGE CONTROLLED OSCILLATOR (RC1 PIN) 2x_Q Q MC88915 REV 6 JULY 10, 2007 ...
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... V CC 120 mW/Device T = 25°C 37.5 mW/Output 300 mW/Device T = 25°C Minimum Maximum — 3.0 (1) FN70 200 36 28.5 50% ± 25% = 5.0 pF) L Guaranteed Minimum MC88915FN55 MC88915FN70 55 70 27.5 35 MC88915 REV 6 JULY 10, 2007 Unit µ 5.0 V Unit ns ns Unit MHz MHz ...
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... CYCLE (470 kΩ From RC1 to An -1.05 -0.50 (470 kΩ From RC1 to An. GND) +1.25 +3.25 — 500 — 750 — 750 1 10 1.5 13.5 , Max. is with C1 = 0.1µF, t Min. is with LOCK LOCK Minimum Unit 9.0 ns 5.0 ns MC88915 REV 6 JULY 10, 2007 Unit ...
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... A 1 MΩ resistor tied to either Analog V GND, depicted in Figure 4, is required to ensure no jitter is present on the MC88915 outputs. This technique causes a phase offset between the SYNC input and the output connected to the FEEDBACK input, measured at the input pins. The t spec describes how this offset PD varies with process, temperature, and voltage ...
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... SKEWr – (ps) + (ps –72 40 –44 276 –40 255 –274 –34 –16 250 –633 –35 limit, and [–0 specification was measured described PD demonstrate this dependence. Figure 5 is from devices repre- = 5.25 V and CC Figure realistic rep MC88915 REV 6 JULY 10, 2007 PD 3.0 V ...
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... Frequency Variation for Q4 Output Fed PD Back, Including Process and Voltage Variation @ 25°C (with 1.0 MΩ Resistor Tied to Analog GND) Figure 5. Graphs 8 2.5 7.5 12.5 17.5 25.0 5.0 10.0 15.0 20.0 22.5 SYNC INPUT FREQUENCY (MHz) Figure 5b (with 1.0 MΩ Resistor Tied to Analog SYNC INPUT FREQUENCY (MHz) Figure 5d MC88915 REV 6 JULY 10, 2007 27 ...
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... Figure 6. Output/Input Switching Waveforms and Timing Diagrams (These waveforms represent the hook-up configuration of TIMING NOTES: 1. The MC88915 aligns rising edges of the FEEDBACK input and SYNC input; therefore, the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as “ ...
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... Q3 2X_Q frequency. 25 MHz “Q” CLOCK Allowable Input Frequency Range: Q2 OUTPUTS 20 MHz to (2X_Q FMAX Spec) (for FREQ_SEL HIGH) 10 MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW) Q1 PLL_EN HIGH Figure 7. Wiring Diagrams 10 MC88915 REV 6 JULY 10, 2007 ...
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... HIGH 10 µF LOW FREQUENCY FREQUENCY BYPASS BYPASS Figure 8. Recommended Loop Filter and Analog Isolation Scheme for the MC88915 NOTES CONCERNING LOOP FILTER AND BOARD LAYOUT ISSUES 1. Figure 8 shows a loop filter and analog isolation scheme which will be effective in most applications. The ...
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... DISTRIBUTE CLOCK @ f CLOCK @ 2f AT POINT OF USE Figure 9. Representation of a Potential Multi-Processing Application Utilizing the MC88915 for Frequency Multiplication and Low Board-to-Board Skew MC88915 SYSTEM LEVEL TESTING FUNCTIONALITY When the PLL_EN pin is low, the VCO is disabled and the 88915 is in low frequency “test mode”. In test mode (with FREQ_SEL high), the 2X_Q output is inverted from the selected SYNC input, and the “ ...
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... MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS IDT™ / ICS™ CMOS PLL CLOCK DRIVERS PACKAGE DIMENSIONS PACKAGE DIMENSIONS CASE 776-02 ISSUE D PLCC PLASTIC PACKAGE 13 MC88915 REV 6 JULY 10, 2007 ...
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... MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 netcom@idt.com 408-284-8200 480-763-2056 Fax: 408-284-2775 Corporate Headquarters Asia Pacific and Japan Integrated Device Technology, Inc. Integrated Device Technology 6024 Silver Creek Valley Road Singapore (1997) Pte ...