sy100el34lzitr Micrel Semiconductor, sy100el34lzitr Datasheet

sy100el34lzitr

Manufacturer Part Number

sy100el34lzitr

Description

Sy10el34 Sy100el34 5v/3.3v ?2, ?4, ?8 Clock Generation Chip

Manufacturer

Micrel Semiconductor

Datasheet

1.SY100EL34LZITR.pdf (5 pages)

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Micrel, Inc.

Precision Edge is a registered trademark of Micrel, Inc.

M9999-031006

hbwhelp@micrel.com or (408) 955-1690

FEATURES

3.3V and 5V power supply options

50ps output-to-output skew

Synchronous enable/disable

Master Reset for synchronization

Internal 75K input pull-down resistors

Available in 16-pin SOIC package

PIN NAMES

CLK

Differential Clock Inputs

Synchronous Enable

Master Reset

Reference Output

Differential 2 Outputs

Differential 4 Outputs

Differential 8 Outputs

Function

5V/3.3V 2, 4, 8 CLOCK

GENERATION CHIP

generation chips designed explicitly for low skew clock

generation applications. The internal dividers are

synchronous to each other, therefore, the common output

edges are all precisely aligned. The devices can be driven

by either a differential or single-ended ECL or, if positive

power supplies are used, PECL input signal. In addition,

by using the V

coupled into the device. If a single-ended input is to be

used, the V

input and bypassed to ground via a 0.01 F capacitor.

The V

reference for the input of the EL34/L under single-ended

input conditions. As a result, this pin can only source/

sink up to 0.5mA of current.

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the divider stages. The

internal enable flip-flop is clocked on the falling edge of

the input clock, therefore, all associated specification

limits are referenced to the negative edge of the clock

input.

state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple EL34/Ls in a system.

DESCRIPTION

The SY10/100EL34/L are low skew

The common enable (EN) is synchronous so that the

Upon start-up, the internal flip-flops will attain a random

output is designed to act as the switching

output should be connected to the CLK

output, a sinusoidal source can be AC-

Precision Edge

SY100EL34/L

Precision Edge

Rev.: H

Issue Date: March 2006

SY10EL34/L

Precision Edge

SY100EL34/L

4, 8 clock

SY10EL34/L

Amendment: /0

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sy100el34lzitr Summary of contents

Page 1

Micrel, Inc. FEATURES 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75K input pull-down resistors Available in 16-pin SOIC package PIN NAMES Pin Function CLK Differential Clock Inputs EN Synchronous Enable MR ...

Page 2

... Z16-2 (2) SY10EL34LZCTR Z16-2 SY100EL34LZC Z16-2 (2) SY100EL34LZCTR Z16-2 SY10EL34LZI Z16-2 (2) SY10EL34LZITR Z16-2 SY100EL34LZI Z16-2 (2) SY100EL34LZITR Z16-2 (3) SY10EL34LZG Z16-2 (2, 3) SY10EL34LZGTR Z16-2 (3) SY100EL34LZG Z16-2 (2, 3) SY100EL34LZGTR Z16-2 Notes: 1. Contact factory for die availability. Dice are guaranteed Tape and Reel. 3. Pb-Free package is recommended for new designs. ...

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sy100el34lzitr Micrel Semiconductor, sy100el34lzitr Datasheet

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