nb6lq572m ON Semiconductor, nb6lq572m Datasheet

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nb6lq572m

Manufacturer Part Number
nb6lq572m
Description
2.5v / 3.3v Differential 4 1 Mux W/input Equalizer To 1 2 Cml Clock/data Fanout / Translator
Manufacturer
ON Semiconductor
Datasheet

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nb6lq572mNR4G
Manufacturer:
ON Semiconductor
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250
NB6LQ572M
2.5V / 3.3V Differential 4:1
Mux w/Input Equalizer to
1:2 CML Clock/Data Fanout
/ Translator
Multi−Level Inputs w/ Internal Termination
Description
Data input multiplexer and a 1:2 CML Clock / Data fanout buffer that
operates up to 6 GHz / 8 Gbps respectively with a 2.5 V or 3.3 V
power supply.
which when placed in series with a Clock / Data path, will enhance the
degraded signal transmitted across an FR4 backplane or cable
interconnect. For applications that do not require Equalization,
consider the NB6L572M, which is pin−compatible to the
NB6LQ572M.
resistors and will accept differential LVPECL, CML, or LVDS logic
levels. The NB6LQ572M incorporates a pair of Select pins that will
choose one of four differential inputs and will produce two identical
CML output copies of Clock or Data.
Channel, Backplane and other Clock/Data distribution applications.
externally loaded and terminated with a 50 W resistor to V
optimized for low skew and minimal jitter.
Pb−Free package. Application notes, models, and support
documentation are available at www.onsemi.com. The NB6LQ572M
is a member of the ECLinPS MAX™ family of high performance
clock products.
Features
© Semiconductor Components Industries, LLC, 2009
November, 2009 − Rev. 0
The NB6LQ572M is a high performance differential 4:1 Clock /
Each INx/INx input pair incorporates a fixed Equalizer Receiver,
The differential Clock / Data inputs have internal 50 W termination
As such, the NB6LQ572M is ideal for SONET, GigE, Fiber
The two differential CML outputs will swing 400 mV when
The NB6LQ572M is offered in a low profile 5x5mm 32−pin QFN
Input Data Rate > 8 Gb/s Typical
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 6 GHz Typical
Random Clock Jitter < 0.8 ps RMS
Low Skew 1:2 CML Outputs, < 15 ps max
4:1 Multi−Level Mux Inputs, accepts LVPECL, CML
LVDS
Input EQ for Backplane and Cable Interconnect
Compensation
150 ps Typical Propagation Delay
CC
1
and are
45 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV Peak−to−Peak,
Typical
Operating Range: V
GND = 0 V
Internal 50 W Input Termination Resistors
V
QFN−32 Package, 5mm x 5mm
40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices
REFAC
Reference Output
See detailed ordering and shipping information on page 9 of
this data sheet.
CASE 488AM
MN SUFFIX
(Note: Microdot may be in either location)
QFN32
1
ORDERING INFORMATION
A
WL
YY
WW
G
32
CC
http://onsemi.com
= 2.375 V to 3.6 V with
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
1
AWLYYWWG
MARKING
DIAGRAM
Q572M
NB6L
NB6LQ572M/D
G

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nb6lq572m Summary of contents

Page 1

... The two differential CML outputs will swing 400 mV when externally loaded and terminated with resistor to V optimized for low skew and minimal jitter. The NB6LQ572M is offered in a low profile 5x5mm 32−pin QFN Pb−Free package. Application notes, models, and support documentation are available at www.onsemi.com. The NB6LQ572M is a member of the ECLinPS MAX™ ...

Page 2

... VREFAC1 IN2 50 W VT2 50 W IN2 VREFAC2 IN3 50 W VT3 50 W IN3 VREFAC3 IN0 1 VT0 2 VREFAC0 3 IN0 4 NB6LQ572M IN1 5 VT1 6 VREFAC1 7 IN1 Figure 2. Pinout: QFN−32 (Top View) EQ0 0 EQ1 1 4:1 MUX EQ2 2 EQ3 3 SEL0 SEL1 Figure 1 ...

Page 3

Table 2. PIN DESCRIPTION Pin Number Pin Name 1, 4 IN0, IN0 LVPECL, CML IN1, IN1 LVDS Input 25, 28 IN2, IN2 29, 32 IN3, IN3 2, 6 VT0, VT1 26, 30 VT2, VT3 15 SEL0 LVTTL/LVCMOS 18 ...

Page 4

Table 3. ATTRIBUTES ESD Protection R − SELx Input Pull−up Resistor PU Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM ...

Page 5

Table 5. DC CHARACTERISTICS CML OUTPUT Symbol Characteristic POWER SUPPLY V Power Supply Voltage CC I Power Supply Current for (Inputs and Outputs Open) CML OUTPUTS (Note 6) V Output HIGH Voltage OH V Output LOW Voltage ...

Page 6

Table 6. AC CHARACTERISTICS V Symbol f Maximum Input Clock Frequency V MAX f Maximum Operating Data Rate NRZ, (PRBS23) DATAMAX f Maximum Toggle Frequency, SELx SEL V Output Voltage Amplitude (@ V OUTPP (Note 12) (Figure 12 ...

Page 7

... Figure 4. Inside Eye Height vs. Input Data Rate (Gbps) at Ambient Temperature (Typical), FR4 = 12” FR4 − 12 Inch Backplane Q Driver Q DJ1 Figure 5. Typical NB6LQ572M Equalizer Application and Interconnect with PRBS23 Pattern at 6.5 Gbps Q AMP (mV CLOCK INPUT FREQUENCY (GHz ...

Page 8

V CC INx 50 W VTx 50 W INx Figure 6. Input Structure IHmax V thmax V ILmax Vth IHmin V thmin V ILmin GND Figure 8. V Diagram ...

Page 9

... NB6LQ572M Differential Driver GND GND Figure 17. Capacitor−Coupled Differential Interface (V *VREFAC bypassed to ground with a 0.01 mF capacitor. Receiver NB6LQ572M V (Receiver Figure 19. Alternative Output Termination Package QFN−32 (Pb−Free) QFN−32 (Pb−Free) http://onsemi.com NB6LQ572M ...

Page 10

... D 5.00 BSC D2 2.950 3.100 3.250 E 5.00 BSC E2 2.950 3.100 3.250 e 0.500 BSC K 0.200 −−− −−− L 0.300 0.400 0.500 5.30 3.20 3.20 5. 0.50 PITCH ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB6LQ572M/D ...

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