w83194br-pt Winbond Electronics Corp America, w83194br-pt Datasheet

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w83194br-pt

Manufacturer Part Number
w83194br-pt
Description
Stepless Via Pt Main Clock Generator
Manufacturer
Winbond Electronics Corp America
Datasheet
W83194BR-PT
WINBOND
STEPLESS VIA PT MAIN CLOCK
GENERATOR
Publication Release Date:April 13, 2005
- I -
Revision 1.1

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w83194br-pt Summary of contents

Page 1

... W83194BR-PT WINBOND STEPLESS VIA PT MAIN CLOCK GENERATOR Publication Release Date:April 13, 2005 - I - Revision 1.1 ...

Page 2

... Register 15: SEL24_48 and CPU to CPUCS skew Control (Default = 04h)....................12 7.16 Register 16: 24, 48, PCI Slew rate control (Default = FFh) ..............................................13 7.17 Register 17: PCI, AGP, REF Slew rate control (Default = FCh).......................................13 7.18 Register 18: IOAPIC, CPUCS Slew rate control (Default = FFh) .....................................13 7.19 Register 19: Winbond Chip ID (Read Only) (Default = 81h).............................................14 W83194BR- ...

Page 3

... CPU 1.0V Electrical Characteristics ..................................................................................17 9.6 AGP Electrical Characteristics ...........................................................................................17 9.7 PCI Electrical Characteristics.............................................................................................18 9.8 24M, 48M Electrical Characteristics ..................................................................................18 9.9 REF Electrical Characteristics............................................................................................18 10. ORDERING INFORMATION..................................................................................................... 19 11. HOW TO READ THE TOP MARKING...................................................................................... 19 12. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 20 13. REVISION HISTORY ................................................................................................................ 21 W83194BR-PT Publication Release Date: April 13, 2005 - III - Revision 1.1 ...

Page 4

... S.S.T. scale to reduce EMI. The W83194BR-PT also has watchdog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. The W83194BR-PT accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. 2. PRODUCT FEATURES • 2 Differential pairs of CPU clock outputs • ...

Page 5

... tio & tro & W83194BR-PT VDDI GND IOAPIC 0 IOAPIC 1 GND VDDCS CPUT_CS CPUC_CS CPUCLKT0 CPUCLKC0 VDDC IREF ...

Page 6

... This is internal 120K pull down. OUT 3.3V PCI clock output. Latched input for MULTSEL at initial power up, internal 120K IN tp120k pull up OUT Low skew (< 250ps) PCI clock outputs. OUT 2.5V PCI/2 clock outputs W83194BR-PT DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: April 13, 2005 Revision 1.1 ...

Page 7

... Pin 12 (MULTISEL0). The table is show as follows. System reset signal when the watchdog is time out. This pin will generate 250ms low phase when the watchdog timer is timeout. Power Down Function. This is power down pin, low active (PD#). Internal 120K pull W83194BR-PT ...

Page 8

... IREF = 2.32mA Rr =475 1% 50 Ω IREF = 2.32mA Rr =475 1% 60 Ω IREF = 2.32mA Rr =475 1% 50 Ω IREF = 2.32mA Rr =475 1% 60 Ω IREF = 2.32mA - 5 - W83194BR-PT DESCRIPTION OUTPUT VOH @ Z CURRENT Ioh=4*IREF 1. Ioh=4*IREF 1. Ioh=5*IREF 1.25V @ 50 Ioh=5*IREF 1. Ioh=6*IREF 1. Ioh=6*IREF 1 ...

Page 9

... W83194BR-PT IOAPIC (MHZ) SPREAD % 17.0 +/-0.25% 17.5 +/-0.25% 18.0 +/-0.25% 18.5 +/-0.25% 19.0 +/-0.25% 19.5 +/-0.25% 20.0 +/-0.25% 20.5 +/-0.25% 18.0 +/-0.25% 18.6 +/-0.25% 16.8 +/-0.25% 17.5 +/-0.25% 18.0 +/-0.25% 18.5 +/-0.25% 19.0 +/-0.25% 19.5 +/-0.25% 20.0 +/-0.25% 20.5 +/-0.25% 16.7 +/-0.25% 17.0 +/-0.25% 17.5 +/-0.25% 15.0 +/-0.25% 15 ...

Page 10

... Invert Power on latched value of FS3 pin. Default: 0 (Read only) Invert Power on latched value of FS2 pin. Default: 0 (Read only) Invert Power on latched value of FS1 pin. Default: 1 (Read only) Invert Power on latched value of FS0 pin. Default: 1 (Read only W83194BR-PT Publication Release Date: April 13, 2005 Revision 1.1 ...

Page 11

... Register 4:MULTISEL1 IOAPIC, AGP Control (1 = Enable Stopped) (Default = 7Fh) BIT PIN NO PWD MULTISEL1 I2C R Reserved Reserved IOAPIC1 output control IOAPIC0 output control AGP2 output control AGP1 output control AGP0 output control W83194BR-PT DESCRIPTION DESCRIPTION DESCRIPTION - 8 - ...

Page 12

... Read this register will return a down count value. DESCRIPTION Programmable N divisor value. Bit 7 ~0 are defined in the Register 10. Test bit 2. Winbond test bit, do not change them. Test bit 1. Winbond test bit, do not change them. Programmable M divisor value W83194BR-PT Publication Release Date: April 13, 2005 Revision 1.1 ...

Page 13

... The equation is VCO freq. = 14.318MHz * (N+4)/ M. When the watchdog timer is timeout, this will be clear. In this time, the frequency is set to hardware default latched or safe frequency set by EN_SFAE_FREQ (Register 0 bit 0). CPU, PCI, AGP, ratio selection. The ratio is shown as following table. Test bit 0. Winbond test bit, do not change them W83194BR-PT ...

Page 14

... Publication Release Date: April 13, 2005 - 11 - W83194BR-PT CPU_CS IOAPIC AGP PCI Ratio Ratio Ratio Ratio ...

Page 15

... MHz, 0->48MHz. Default is 48Mhz 0 Reserved 0 0:normal mode, 1: fix mode 0 AGP & PCI FIX frequency (PCI = AGP/2) SEL [1:0] for AGP 0 00: 72MHZ 10: 77NHZ 1 CPU to CPUCS Skew, Skew resolution is 340ps Expand the skew direction is same as 0 CPU_CPUCS_SKEW [2:0] setting W83194BR-PT 01:64MHZ 11: 67MHZ ...

Page 16

... PWD 1 Pin 46,45, IOAPIC [0:1] clock slew rate control 11: strong, 10: normal, 01:normal, 00:weak 1 1 Pin 41,42 CPUC/T_CS clock slew rate control 11: strong, 10: normal, 01:normal, 00:weak 1 1 Reserved 1 1 Reserved W83194BR-PT DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: April 13, 2005 Revision 1.1 ...

Page 17

... MAS_ID [1] 6 MAS_ID [0] 5 SUB_ID [1] 4 SUB_ID [0] 3 MAS_VER_ID [1] 2 MAS_VER_ID [0] 1 SUB_VER_ID [1] 0 SUB_VER_ID [0] 1 Winbond Chip ID. W83194BR-PT is 0x81. 0 Winbond Chip ID. 0 Winbond Chip ID. 0 Winbond Chip ID. 0 Winbond Chip ID. 0 Winbond Chip ID. 0 Winbond Chip ID. 1 Winbond Chip ID. 0 MASK definition for master body ...

Page 18

... ACCESS INTERFACE The W83194BR-PT provides I W83194BR-PT is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I address is defined at 0xD2. Block Read and Block Write Protocol 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 8’h00 8.3 Byte Write protocol 8 ...

Page 19

... W83194BR-PT RATING -0.5V to +4. 4.6 V 3.135V to 3.465V 3.135V to 3.465V - 65° 150°C - 55° 125°C 0° 70°C 2000V TEST CONDITIONS All outputs using 3.3V power All outputs using 3.3V power CPU = 100 to 200 MHz PCI = 33.3 Mhz with load TEST CONDITIONS Measured at 1 ...

Page 20

... C, Test load, Cl=10pF, MIN. MAX. UNITS 500 2000 ps Measure from 0.4V to 2.4V 500 2000 ps Measure from 2.4V to 0.4V 250 ps Measure 1.5V point -33 mA Vout=1.0V -33 mA Vout=3.135V 30 mA Vout=1.95V 38 mA Vout=0. W83194BR-PT TEST CONDITIONS TEST CONDITIONS TEST CONDITIONS Publication Release Date: April 13, 2005 Revision 1.1 ...

Page 21

... W83194BR-PT TEST CONDITIONS Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V TEST CONDITIONS Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V TEST CONDITIONS Measure from 0.4V to 2.4V Measure from 2 ...

Page 22

... PART NUMBER W83194BR-PT 11. HOW TO READ THE TOP MARKING W83194BR-PT 28051234 342GADSA 1st line: Winbond logo and the type number: W83194BR-PT 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 G 320: packages made in '2003, week 42 G: assembly house ID ...

Page 23

... PACKAGE DRAWING AND DIMENSIONS W83194BR- ...

Page 24

... All of the versions before 0.50 are for internal use. n.a. First published preliminary version. 11, 12 Modify register 14,15 descriptions 4, 7~13 Modify register 15, add some descriptions Correction IC version, correction some description and default value Update on Web 21 Add disclaimer Important Notice Publication Release Date: April 13, 2005 - 21 - W83194BR-PT DESCRIPTION Revision 1.1 ...

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