w83194br-sd Winbond Electronics Corp America, w83194br-sd Datasheet - Page 16

• Manufacturer Part Number: w83194br-sd
• Description: Winbond Clock Generator For Intel P4 Springdale Series Chipset
• Manufacturer: Winbond Electronics Corp America

7.13 Register 12: Divider Ratio (Default = C6H)
Table-2 CPU, SRC, AGP, PCI divider ratio selection Table
7.14 Register 13: Control (Default = 0FH)
BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
Bit3/Bit6
Bit1/
EN_MN_PROG
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
IVAL<3>
IVAL<2>
IVAL<1>
IVAL<0>
Reserve
Reserve
Reserve
SRC_H
NAME
NAME
DS9
DS5
DS4
DS3
DS2
DS1
DS0
LSB
0
1
PWD
PWD
1
1
0
0
0
1
1
0
0
0
0
0
1
1
1
1
Div2
Div4
0
1: Program all clock frequency by changing M/N value
SRC frequency select, 1: 100 MHz, 0: 200 MHz
Define the AGP divider ratio,
Table-2 integrate the all divider configuration
Define the AGP divider ratio
Table-2 integrate the all divider configuration
Define the SRC divider ratio
Refer to Table-2
Define the SRC divider ratio
Refer to Table-2
0: Output frequency depend on frequency table
The equation is VCO =14.318MHz*(N+4)/ M.
Once the watchdog timer timeout, the bit will be clear. Then the
frequency will be decided by hardware default FS<4:0> or desired
frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ
(Reg9 - bit 7).
Reserved
Reserved
Charge pump current selection
CPU
Bit0
Div3
Div5
1
Div2
Div4
W83194BR-SD/W83194BG-SD
- 12 -
0
SRC
Bit2
Div3
Div5
1
DESCRIPTION
DESCRIPTION
Div10
Div5
00
Div12
Div6
01
Bit5, 4
AGP
Div12
Div7
10
Div12
Div8
11