w83194br-619 Winbond Electronics Corp America, w83194br-619 Datasheet
w83194br-619
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w83194br-619 Summary of contents
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... W83194BR-619 W83194BG-619 Winbond Clock Generator For INTEL P4 Springdale Series Chipset Date: Mar/28/2006 Revision: 0.7 ...
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... CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET W83194BR-619/W83194BG-619 Data Sheet Revision History PAGES DATES 1 n.a. 2 n.a. 08/01/2003 7~15, 3 10/27/2004 18~20 4 03/28/2006 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. ...
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... Table-2 CPU, SRC, AGP divider ratio selection Table .............................................................13 7.16 Register 13: Control Register (Default =0FH)............................................................................14 7.17 Register 14: Control Register (Default =32H)............................................................................14 7.18 Register 15: Control Register (Default =3AH) ...........................................................................15 7.19 Register 16: Control Register (Default =24H)............................................................................15 7.20 Register 17: Slew Rate Control Register (Default =55H)..........................................................15 7.21 Register 18: Slew Rate Control (Default =55H).........................................................................16 W83194BR-619/W83194BG-619 - II - ...
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... Skew Group timing clock............................................................................................................20 9.4 CPU 0.7V Electrical Characteristics...........................................................................................20 9.5 SRC 0.7V Electrical Characteristics...........................................................................................20 9.6 3V66 Electrical Characteristics...................................................................................................21 9.7 PCI Electrical Characteristics .....................................................................................................21 9.8 24M, 48M Electrical Characteristics...........................................................................................21 9.9 REF Electrical Characteristics....................................................................................................22 9.10 ORDERING INFORMATION .....................................................................................................22 9.11 How to read the top marking ......................................................................................................23 10. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 24 W83194BR-619/W83194BG-619 Publication Release Date: March, 2006 - III - Revision 0.7 ...
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... The W83194BR-619 also has watchdog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. The W83194BR-619 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. 2. PRODUCT FEATURES • 2 pairs current mode differential clock for CPU and Chipset • ...
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... VDDPCI PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDPCI PCICLK5 PCICLK6 PCICLK7 & SEL24_48# /24_48MHz & FS3 /48MHz #: Active low *: Internal pull up resistor 120KΩ to VDD & : Internal Pull-down resistor 120KΩ to GND W83194BR-619/W83194BG-619 XIN 4 XOUT 5 GND GND ...
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... < > & & W83194BR-619/W83194BG-619 tru tio ...
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... PCICLK_F0 7 & FS2 PCICLK7_F1 8 & FS4 W83194BR-619/W83194BG-619 DESCRIPTION Input Latch input pin and internal 120KΩ pull down Latch input pin and internal 120KΩ pull up Output Open Drain Bi-directional Pin Bi-directional Pin, Open Drain Active Low Internal 120kΩ pull-up Internal 120kΩ ...
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... I2C Control Interface PIN PIN NAME 33 SDATA* 32 SCLK* W83194BR-619/W83194BG-619 TYPE OUT 3.3V 33MHz PCI clock outputs. OUT 3.3V 33MHz PCI clock outputs. OUT 14.318MHz output. Latched input for FS1 at initial power up for H/W selecting the tp120k output frequency clocks. This is internal 120KΩ pull up. ...
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... VDD48 28 VDD3V66 35 VDD 41 VDDCPU 48 VDDA 6,11,18,24,29,38,44,47 GND W83194BR-619/W83194BG-619 Deciding the reference current for the CPUCLK pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current. The table is show as follows. Board Target Reference R, Trace Iref 50 Ohms R=475 Iref=2.32mA System reset signal when the watchdog is time out ...
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... W83194BR-619/W83194BG-619 FS0 CPU (MHZ) SRC (MHZ) 0 100.0 100/200 1 200.0 100/200 0 133.3 100/200 1 166.6 100/200 0 200.0 100/200 1 400.0 100/200 0 266.6 100/200 1 333.3 100/200 0 100.9 100/200 1 202 ...
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... FS2 X 1 FS1 X 0 FS0 X W83194BR-619/W83194BG-619 DESCRIPTION Software frequency table selection through I Enable software table selection FS [4:0 Hardware table setting (Jump mode Software table setting through Bit7~3. (Jump less mode) Enable spread spectrum mode under clock output Spread Spectrum mode disable ...
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... REF0 1 1 MODE1 0 0 MODE0 0 W83194BR-619/W83194BG-619 DESCRIPTION Pin 10 PCI_F2 output control Pin 9 PCI_F1 output control Pin 8 PCI_F0 output control Pin 21 PCICLK7 output control Pin 20 PCICLK6 output control Pin 19 PCICLK5 output control Pin 16 PCICLK4 output control Pin 15 PCICLK3 output control DESCRIPTION ...
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... These bits will be reloaded in Reg-0 to select frequency table. As the 2 SAF_FREQ [2] 0 watchdog is timeout and EN_SAFE_FREQ=1. 1 SAF_FREQ [ SAF_FREQ [0] 0 W83194BR-619/W83194BG-619 CPU OVER CLOCK MODE 00 01 Byte 8 & 9 Byte 4 & 10 (asynchronous) Byte 4 & 10 (asynchronous) CPU is effective Only. DESCRIPTION MHz output selection ...
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... Reserve 0 1 ASEL<1> ASEL<0> 0 W83194BR-619/W83194BG-619 DESCRIPTION Setting the down count depth. One bit resolution represents 250ms. Default time depth is 8*250ms = 2.0 second. If the watchdog timer is counting, this register will return present down count value. DESCRIPTION Tri-state all output if set 1 Reserved Reserved ...
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... Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register 7. 3 N_DIV [ N_DIV [ N_DIV [ N_DIV [0] 0 7.12 Register 10: M/N Program Register (Default =13H) BIT NAME PWD 7 Reserve 0 Reserved 6 N3<6> N3<5> N3<4> 1 Programmable N3 divisor bit 6 ~0 for synchronism 3 N3<3> 0 SRC/AGP/PCI clock. 2 N3<2> N3<1> N3<0> 1 W83194BR-619/W83194BG-619 DESCRIPTION DESCRIPTION DESCRIPTION - 12 - ...
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... MSB Bit1/ 0 Div2 Bit3/ 1 Div4 Bit6 W83194BR-619/W83194BG-619 DESCRIPTION Spread Spectrum Up Counter bit 3 ~ bit 0. Spread Spectrum Down Counter bit 3 ~ bit 0 2’s complement representation. Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000 DESCRIPTION SRC frequency select, 1: 100MHz, 0: 200MHz Define the AGP divider ratio, ...
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... SPCNT [ SPCNT [0] 0 W83194BR-619/W83194BG-619 DESCRIPTION 0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. Once the watchdog timer timeout, the bit will be clear. Then the frequency will be decided by hardware default FS<4:0> or desired frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ (Reg9 - bit 7) ...
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... AGP_32_S2 0 2 AGP_32_S1 1 1 AGP_10_S2 0 0 AGP_10_S1 1 W83194BR-619/W83194BG-619 DESCRIPTION Invert the CPU phase 0: Default, 1: Inverse Reserved Reserved Spread Spectrum type select. 00: Down 1% 01: Down 0.5% 10: Center ± 0.5% 11: Center ± 0.25% CPU to AGP skew control. Skew resolution is 300ps The decision of skew direction is same as ASKEW [2:0] setting ...
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... PCI4, 3,2 slew rate control 11: Strong, 00: Weak, 10/01: Normal PCI1, 0 slew rate control 11: Strong, 00: Weak, 10/01: Normal REF slew rate control 11: Strong, 00: Weak, 10/01: Normal DESCRIPTION PWD 0 Winbond Chip ID. W83194BR-619 (SA5847). 1 Winbond Chip ID. 0 Winbond Chip ID. 0 Winbond Chip ID. 0 Winbond Chip ID. 1 Winbond Chip ID. ...
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... MASK version definition for master body *A****001AA: 00, *A****001AB: 01, 2 MAS_VER_ID [0] 0 *A****001AC: 10, *A****001AD: 11. MASK version definition for code body 1 SUB_VER_ID [1] 0 *A****001A: 00, *A****001B: 01 *A****001C: 10, *A****001D: 11 W83194BR-619/W83194BG-619 DESCRIPTION *A****002: 10, *A****003: 11, *A****004:00 Publication Release Date: March, 2006 - 17 - Revision 0.7 ...
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... CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET 8. ACCESS INTERFACE The W83194BR-619 provides I W83194BR-619 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I address is defined at 0xD2. Block Read and Block Write Protocol 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 00H 8 ...
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... Input ESD protection (Human body model) 9.2 General Operating Characteristics VDDREF=VDDA=VDDCPU=VDD3V66=VDDPCI=VDD48= 3.3V Cl=10pF PARAMETER SYMBOL Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance W83194BR-619/W83194BG-619 MIN MAX UNITS ...
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... Cycle to Cycle jitter Duty Cycle 9.5 SRC 0.7V Electrical Characteristics ± VDD= 3. Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF PARAMETER Rise Time Fall Time Absolute crossing point Voltages Cycle to Cycle jitter Duty Cycle W83194BR-619/W83194BG-619 MIN TYP MAX UNITS 1.5 2.6 3.5 ns 100 ps 250 ps 500 ps 1000 ps ...
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... VDD48= 3. +70 PARAMETER Rise Time Fall Time Long term jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max W83194BR-619/W83194BG-619 ° ° +70 C, Test load, Cl=10pF, MIN MAX UNITS 500 2000 ps Vol=0.4V, Voh=2.4V ...
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... Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 9.10 ORDERING INFORMATION PART NUMBER W83194BR-619 W83194BG-619 W83194BR-619/W83194BG-619 ° ° +70 C, Test load, Cl=10pF, MIN MAX UNITS 1000 4000 ps Vol=0.4V, Voh=2.4V ...
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... CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET 9.11 How to read the top marking 1st line: Winbond logo and the type number: W83194BR-619/W83194BG-619 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 420 ...
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... CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET 10. PACKAGE DRAWING AND DIMENSIONS Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. W83194BR-619/W83194BG-619 - 24 - ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83194BR-619/W83194BG-619 Important Notice Publication Release Date: March, 2006 - 25 - ...