w83194br-39b Winbond Electronics Corp America, w83194br-39b Datasheet

no-image

w83194br-39b

Manufacturer Part Number
w83194br-39b
Description
Step-less 3-dimm Clock
Manufacturer
Winbond Electronics Corp America
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W83194BR-39B
Quantity:
15
Company:
Part Number:
W83194BR-39B
Quantity:
528
1.0 GENERAL DESCRIPTION
The W83194BR-39B is a Clock Synthesizer which provides all clocks required for high-speed RISC or
CISC microprocessor such as Intel Pentium II or Pentium III. W83194BR-39B provides 64 CPU/PCI
frequencies which are selectable with smooth transitions by hardware or software. W83194BR-39B
also provides 13 SDRAM clocks controlled by the none-delay buffer_in pin.
The W83194BR-39B provides step-less frequency programming by controlling the VCO freq. and the
programmable PCI clock output divisor ratio. A watch dog timer is quipped and when time out, the
RESET# pin will output 4ms pulse signal.
The W83194BR-39B accepts a 14.318 MHz reference crystal as its input. Spread spectrum built in at
±0.5% or ±0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency
selection through I
CPU and PCI clocks be stable within 2 ms after power-up. Using dual function pin for the slots(ISA,
PCI, CPU, DIMM) is not recommend.
2.0 PRODUCT FEATURES
Supports Pentium
2 CPU clocks (one free-running CPU clock)
13 SDRAM clocks for 3 DIMMs
6 PCI synchronous clocks
One IOAPIC clock for multiprocessor support
Optional single or mixed supply:
< 250ps skew among CPU and SDRAM clocks
< 250ps skew among PCI clocks
< 5ns propagation delay SDRAM from buffer input
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VddL2 = 2.5V)
MODE pin for power Management
RESET# out when watch dog timer time out
One 48 MHz for USB & one 24 MHz for super I/O
±0.25% or ±0.5% spread spectrum function to reduce EMI in freq. table mode
Programmable spread spectrum in the M/N step-less mode
Programmable registers to enable/stop each output and select modes
Skew from CPU (earlier) to PCI clock 1 to 4ns, center 2.6ns.
Smooth frequency switch with selections from 66 MHz to 200 MHz CPU
Step-less frequency programming by controlling the VCO freq. and the clock output divisor ratio
I
2
C 2-Wire serial interface and I
2
C interface. The device meets the Pentium power-up stabilization, which requires
II and !!! CPU with I
2
C read back
2
C.
- 1 -
STEP-LESS 3-DIMM CLOCK
Publication Release Date: June 2000
W83194BR-39B
Revision 0.46

Related parts for w83194br-39b

w83194br-39b Summary of contents

Page 1

... PCI clock output divisor ratio. A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal. The W83194BR-39B accepts a 14.318 MHz reference crystal as its input. Spread spectrum built in at ±0.5% or ±0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency ...

Page 2

... RESET SDRAM12 10 39 Vss 11 38 SDRAM SDRAM Vddq3 14 SDRAM SDRAM Vss 17 SDRAM SDRAM Vddq3 20 SDRAM SDRAM Vddq4 27 23 48MHz/FS0 24MHz/FS1* Publication Release Date: June 2000 - 2 - W83194BR-39B PRELIMINARY Revision 0.46 ...

Page 3

... Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU and PCI clocks. OUT Low skew (< 250ps) PCI clock outputs. PCICLK 0:3 are double strength pins PCICLK 4 is not Inputs to fanout for SDRAM outputs W83194BR-39B PRELIMINARY FUNCTION FUNCTION Publication Release Date: June 2000 Revision 0.46 ...

Page 4

... Power supply for CPUCLK[0:3], either 2.5V or 3.3V Power supply for PCICLK_F, PCICLK[0:4], 3.3V. Power supply for SDRAM[0:12], and CPU PLL core, nominal 3.3V. 27 Power for 24 & 48MHz output buffers and fixed PLL core W83194BR-39B PRELIMINARY FUNCTION 2 C 2-wire control interface 2 C 2-wire control interface FUNCTION FUNCTION Publication Release Date: June 2000 Revision 0 ...

Page 5

... CPU(MHz) SDRAM(MHz) 80.00 80.00 75.00 75.00 83.30 83.30 66.82 66.82 103.00 103.00 112.00 112.00 68.01 68.01 100.23 100.23 120.00 120.00 115.00 115.00 120.00 120.00 105.00 105.00 140.00 140.00 155.00 155.00 124.00 124.00 133.30 133. W83194BR-39B PRELIMINARY PCI(MHz) 40.00 37.50 41.65 33.41 34.33 37.34 34.01 33.41 30.00 38.33 40.00 35.00 35.00 38.75 31.00 33.30 Publication Release Date: June 2000 Revision 0.46 ...

Page 6

... All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. W83194BR-39Binitializes with default register settings. Use of the 2-wire control interface is then optional. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer ...

Page 7

... W83194BR-39B PRELIMINARY byte must be sent following the PCI(MHz) 40.00 37.50 41.65 33.41 34.33 37.34 34.01 33.41 30.00 38.33 40.00 35.00 35.00 38.75 31.00 33.30 40.00 31.75 32.50 33.75 34.00 34.25 34.75 35.00 35.25 35.50 35.75 Publication Release Date: June 2000 Revision 0.46 ...

Page 8

... W83194BR-39B PRELIMINARY 36.00 36.25 36.50 37.00 37.25 PCI(MHz) 37.75 38.00 38.25 38.50 38.75 39.00 39.25 39.50 39.75 40.50 32.60 32.80 33.00 33.40 33.60 33.80 34.00 34.40 34.80 35.20 35.60 36.00 36.40 36.80 37.20 37.60 38.00 38.40 38.80 Publication Release Date: June 2000 Revision 0.46 ...

Page 9

... Selection by software Running 1 = Tristate all outputs Description Reserved Reserved 0 = Normal 1 = Spread Spectrum enabled 0 = ±0.25% Spread Spectrum Modulation 1 = ±0.5% Spread Spectrum Modulation SDRAM12 (Active / Inactive) Reserved CPUCLK1 (Active / Inactive) CPUCLK_F (Active / Inactive W83194BR-39B PRELIMINARY 196.00 39.20 198.00 39.60 200.00 40.00 Description ...

Page 10

... REF0 (Active / Inactive) 48MHz (Active / Inactive) 24MHz (Active / Inactive) IOAPIC (Active / Inactive) SDRAM(8:11) (Active / Inactive) SDRAM(4:7) (Active / Inactive) SDRAM(0:3) (Active / Inactive) Reserved Latched FS3# Latched FS2# Latched FS1# Latched FS0 W83194BR-39B PRELIMINARY Description Description Description Publication Release Date: June 2000 Revision 0.46 ...

Page 11

... Reserved Reserved Reserved Reserved Description Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Description Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Version W83194BR-39B PRELIMINARY Publication Release Date: June 2000 Revision 0.46 ...

Page 12

... Winbond Version Winbond Version Winbond Version ID W83194BR-39B Publication Release Date: June 2000 - 12 - PRELIMINARY Revision 0.46 ...

Page 13

... JA BW 500 J 0.4 1.6 t TLH t THL V 0.7 1.5 over V 0.7 2.1 RBE - 13 - W83194BR-39B PRELIMINARY Rating - 0 7 150 125 + Units Test Conditions % Measured at 1. Load Measured at 1. Load Measured at 1. KHz Load on CPU and PCI ...

Page 14

... Ioz 10 I dd3 I dd2 CPUS3 CPUS2 I PD3 - 14 - W83194BR-39B PRELIMINARY = + Units Test Conditions All outputs V dc All outputs using 3.3V power CPU = 66.6 MHz PCI = 33.3 Mhz with load mA Same as above mA ...

Page 15

... OH(min) -27 OH(max) I OL(min OL(max) 0.4 RF(min) 1.6 RF(max) Min Typ Max -29 OL(min) 28 OL(max) 0.4 RF(min) 1.8 RF(max W83194BR-39B PRELIMINARY Units Test Conditions mA Vout = 1 Vout = 2.0V mA Vout = 1 Vout = 0 10pF Load ns 20pF Load Units Test Conditions mA Vout = 1 Vout = 2 Vout = 1 Vout = 0.2 V ...

Page 16

... Typ Max -46 OL(min) 53 OL(max) 0.5 RF(min) 1.3 RF(max) Min Typ Max -33 -33 30 OL(min) 38 OL(max) 0.5 RF(min) 2.0 RF(max W83194BR-39B PRELIMINARY Units Test Conditions mA Vout = 1 Vout = 3.135V mA Vout = 1. Vout = 0 10pF Load ns 20pF Load Units Test Conditions mA Vout = 1. Vout = 3.135 V mA Vout = 1. Vout = 0 ...

Page 17

... Output pull-low Output tri-state Within 3ms Input Output Output pull-low Output tri-state @3.3V ) inside. The default state will be logic resistor should be placed before the serious terminating resistor. Note - 17 - W83194BR-39B PRELIMINARY Vdd resistor is recommended to be Publication Release Date: June 2000 Revision 0.46 ...

Page 18

... Terminating Resistor Device Pin 10k Ground Programming Header Vdd Pad Ground Pad Series 10k Terminating Resistor Device Pin - 18 - W83194BR-39B PRELIMINARY Clock Trace EMI Reducing Cap Optional Ground Clock Trace EMI Reducing Cap Optional Ground Publication Release Date: June 2000 Revision 0.46 ...

Page 19

... W83194BR-39B 11.0 HOW TO READ THE TOP MARKING W83194BR-39B 28051234 814GBA 1st line: Winbond logo and the type number: W83194BR-39B 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 814: packages made in '98, week 14 G: assembly house ID ...

Page 20

... Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Publication Release Date: June 2000 - 20 - W83194BR-39B PRELIMINARY Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 ...

Related keywords