APP750NP Agere Systems, APP750NP Datasheet

APP750NP

Manufacturer Part Number

APP750NP

Description

10G Network Processor Chip Set (APP750NP And APP750TM)

Manufacturer

Agere Systems

Datasheet

1.APP750NP.pdf (3 pages)

Current page: 1 of 3
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10G Network Processor Chip Set (APP750NP and APP750TM)

Introduction

The Agere Systems PayloadPlus

Processor chip set provides wire-speed deep-

packet processing for high performance packet-

processing systems. This software-compatible,

programmable chip set consists of two chips—

the APP750NP classification engine (NP10) and

the APP750TM traffic manager (TM10)—and

follows the successful Agere Systems 2.5G

PayloadPlus chip set.

This 10G chip set provides full carrier-class

packet processing functionality, including

classification, policing, statistics, queueing,

scheduling, shaping, buffer management and

packet/cell modification. A three-chip

configuration—one NP10 and two TM10s—

provides full duplex 10 Gb/s packet processing

OUT

PHY

PORT CARD

FBP = Fabric Backpressure

PCI = PCI bus to Host CPU

Framer

SPI4

10G Network Processor System Diagram

10G Network

SPI4 = POS-PHY Level 4 interface

SERDES = high-speed serial interface

TM10

NP10

PCI

SPI4

functionality. An additional NP10 can be added if

egress classification is required. The 10G

PayloadPlus solution requires only DRAM and a

small amount of SRAM for external memory to

provide high-performance functionality. No

content addressable memory (CAM) is required.

The chip set supports complex packet

classification policies, including multifield IPv4/

IPv6 classification, PPPoE, L2TP, MPLS, etc.,

with a large amount of headroom for future

classification needs. OEMs use the Agere

Systems high-level Functional Programming

Language (FPL) to specify packet classification

policies. Statistics, policing, and packet

modification functions are performed by on-chip

compute engines that are programmed using the

C-like Agere Scripting Language (ASL).

PCI 2.2 32/64 33/66

(optional)

TM10

NP10

FBP

SERDES

SPI4

10x2.5GSERDES

Switch

Fabric

November 2002

Host

CPU

Product Brief

Related parts for APP750NP

APP750NP Summary of contents

Page 1

... Network Processor Chip Set (APP750NP and APP750TM) Introduction The Agere Systems PayloadPlus Processor chip set provides wire-speed deep- packet processing for high performance packet- processing systems. This software-compatible, programmable chip set consists of two chips— the APP750NP classification engine (NP10) and the APP750TM traffic manager (TM10)— ...

Page 2

... OEMs can readily interface to a wide variety of switch fab- rics with minimal glue logic effort. Support for simple interface to third-party fabrics using the I off-the-shelf FPGAs Complete Agere Systems 10G fiber-to-fabric line card I reference design with supporting software FPGA-based hardware emulation system and software I simulator provides complete pre-silicon hardware and software development support ...

Page 3

... Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems, Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. PayloadPlus is a trademark of Agere Systems, Inc. PayloadPlus is a registered trademark of Agere Systems Inc. ...

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