pi90sd1636 Pericom Semiconductor Corporation, pi90sd1636 Datasheet

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pi90sd1636

Manufacturer Part Number
pi90sd1636
Description
Ic Serdes Gig Eth Txrx 64-lqfp
Manufacturer
Pericom Semiconductor Corporation
Datasheet

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Features
• IEEE 802.3z Gigabit Ethernet Compliant
• Supports 1.25 Gbps Using NRZ Coding over uncompensated
• Fully integrated CMOS IC
• Low Power Consumption
• ESD rating >2000V (Human Body Model) or > 200V (Ma-
• 5-Volt Input Tolerance
• Pin-Compatible with Agilent HDMP1636A/HDMP- 1646A
• Packaging (Pb-free & Green available):
Applications
• Gigabit Ethernet
• Serial Backplane
• Proprietary point-to-point applicaitons
twin coax cable
chine Model)
and Vitesse VSC7123 transceivers (see Appendix A)
- 64-pin LQFP (FC)
- 64-pin LQFP (FD)
1
Description
The PI90SD1636A is a single chip, Gigabit Ethernet transceiver.
It performs all the functions of the Physical Medium Attachment
(PMA) portion of the Physical layer, as specified by the IEEE
802.3z Gigabit Ethernet standard. These functions include parallel-
to-serial and serial-to-parallel conversion, clock generation, clock
data recovery, and word synchronization. In addition, an internal
loopback function is provided for system debugging.
The PI90SD1636A is ideal for Gigabit Ethernet, serial backplane
and proprietary point-to-point applications. The device sup-
ports 1000BASE-LX and 1000BASE-SX fiber-optic media, and
1000BASE-CX copper media.
The transmitter section of the PI90SD1636A accepts 10-bit wide
parallel TTL data and converts it to a high speed serial data stream.
The parallel data is encoded in 8b/10b format. This incoming
parallel data is latched into an input register, and synchronized
on the rising edge of the 125 MHz reference clock supplied by
the user. A phase locked loop (PLL) locks to the 125 MHz clock.
The clock is then multiplied by 10 to produce a 1.25 GHz serial
clock that is used to provide the high speed serial data output. The
output is sent through a Pseudo Emitter Coupled Logic (PECL)
driver. This output connects directly to a copper cable in the case
of 1000BASE-CX medium, or to a fiber optic module in the case
of 1000BASE-LX or 1000BASE SX fiber optic medium.
The receiver section of the PI90SD1636A accepts a serial PECL-
compatible data stream at a 1.25 Gbps rate, recovers the original
10-bit wide parallel data format, and retimes the data. A PLL locks
onto the incoming serial data stream, and recovers the 1.25 GHz
high speed serial clock and data. This is accomplished by con-
tinually frequency locking onto the 125 MHz reference clock, and
by phase locking onto the incoming data stream. The serial data
is converted back to parallel data format. The ‘comma’ character
is used to establish byte alignment. Two 62.5 MHz clocks, 180
degrees out of phase, are recovered. These clocks are alternately
used to clock out the parallel data on the rising edge. This parallel
data is sent to the user in TTL-compatible form.
SERDES Gigabit Ethernet Transceiver
PI90SD1636A
PS8641
10/14/04

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pi90sd1636 Summary of contents

Page 1

... SX fiber optic medium. The receiver section of the PI90SD1636A accepts a serial PECL- compatible data stream at a 1.25 Gbps rate, recovers the original 10-bit wide parallel data format, and retimes the data. A PLL locks onto the incoming serial data stream, and recovers the 1 ...

Page 2

... Functional Block Diagram EWRAP TX<9:0> TX_CLK RX_CLK<1> RX_CLK<0> 10 RX<9:0> EN_CDET COM_DET 10 10 Input Data Shift Registers Latch TX PLL Clock 62.5 MHz ÷ 2 62.5 MHz 125 MHz RX PLL Clock Output Latch 10 10 Shift FRAME ENABLE Registers 2 SERDES Gigabit Ethernet Transceiver DOUT+ DOUT- Generator Recovery DIN+ DIN- PI90SD1636A PS8641 10/14/04 ...

Page 3

... TTL_IN TTL Input TTL_OUT TTL Output HS_IN Hight-Speed Input HS_OUT High-Speed Output P Power Ground Definition 3 PI90SD1636A SERDES Gigabit Ethernet Transceiver COM_DET 46 GND_RXT 45 RX<0> 44 RX<1> 43 RX<2> 42 ...

Page 4

... Receiver Byte Clocks. Two 180 degrees out-of-phase 62.5 MHz clock signals that are recovered by the receiver section. The received bytes are alternately clocked by the rising edges of these signals. The rising edge of RX_CLK<1> aligns with a comma character when detected. 4 PI90SD1636A SERDES Gigabit Ethernet Transceiver PS8641 10/14/04 ...

Page 5

... Power supply to line driver circuits. Ground supply is from pin 64. High-speed serial data output. These pins are active when EWRAP is disabled and are held static at logic 1 when EWRAP is enable. Power and ground pair for high-speed transmit logic in the parallel-to-serial section. 5 PI90SD1636A SERDES Gigabit Ethernet Transceiver Description PS8641 10/14/04 ...

Page 6

... Clock Recovery The serial input data stream contains both data and clock. The clock recovery block is used to extract both data and clocks from this input. In addition to data, two clocks of 62.5 MHz are recovered. SERDES Gigabit Ethernet Transceiver 6 PI90SD1636A PS8641 10/14/04 ...

Page 7

... T = 0°C to +70° 3.15V to 3.45V A CC Parameter 7 PI90SD1636A SERDES Gigabit Ethernet Transceiver Stresses above those listed under Absolute Units Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and correct V functional operation of the device at ...

Page 8

... +70 A Min. 1.5 1.0 8 SERDES Gigabit Ethernet Transceiver Min. Typ 2.2 0 220 = 3.15V to 3.45V CC Min. Typ. Max. 125 -100 +100 3.15V to 3.45V CC Typ. Max. 3.5 4.4 PI90SD1636A Max. Unit 5.5 0 0.6 40 μA -600 mA Unit MHz ppm Unit ns bits PS8641 10/14/04 ...

Page 9

... SERDES Gigabit Ethernet Transceiver DATA DATA t HOLD Figure 3. Transmitter Section Timing DATA BYTE A t_TXLAT DATA BYTE B Figure 4. Transmitter Latency T = 0°C to +70° 3.15V to 3.45V A CC Min. 2.5 1.5 40 7.5 9 PI90SD1636A 1.4V 2.0V DATA DATA 0.8V DATA BYTE B DATA BYTE C 1.4V Typ. Max. Unit 2500 bits 500 60 8.5 22.4 28.0 bits PS8641 µ ...

Page 10

... COM_DET RX_CLK<0> DATA BYTE C DIN ± RX<9:0> RX_CLK<1>/<0> t HOLD DATA DATA Figure 5. Receiver Section Timing DATA BYTE t_rxlat DATA BYTE A Figure 6. Receiver Latency 10 PI90SD1636A SERDES Gigabit Ethernet Transceiver DATA DATA t A DATA BYTE D PS8641 1.4V 2.0V 0.8V 2.0V 0.8V 1.4V 1.4V 10/14/04 ...

Page 11

... Packaging Mechanical: 64-pin LQFP (FC) .472 12.00 BSC Square .004 0.10 Seating Plane .007 0.17 0.27 .010 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS .394 10.00 BSC Square 1.60 .063 Max. .053 .057 .019 .002 1.35 0.50 BSC .006 1.45 0.05 0.15 11 PI90SD1636A SERDES Gigabit Ethernet Transceiver .004 .008 0.09 0.20 GAUGE PLANE .018 0.45 0.75 .030 1.00 REF .039 PS8641 10/14/04 ...

Page 12

... Package Code FC 64-pin 10mm x10mm LQFP FC Pb-free & Green, 64-pin 10mm x10mm LQFP FD 64-pin 14mm x14mm LQFP FD Pb-free & Green, 64-pin 14mm x14mm LQFP 12 PI90SD1636A SERDES Gigabit Ethernet Transceiver .004 .008 0.09 0.20 GAUGE PLANE 0.45 .018 0.75 .030 1.00 REF .039 Package Description PS8641 ...

Page 13

... Minor differences exist amongst the parts regarding the use of certain pins that are used by the manufacturer for internal tests further clarified below. These differences will not affect plug compatibility during normal operations. Appendix A Gigabit Ethernet Transceiver Pin Cross Reference Guide PI90SD1636A, VSC7123 and HDMP1636A/1646A Summary: is functionally pin compatible with Vitesse’s VSC7123 and Agilent’s HDMP-1636A/46A. 13 PI90SD1636A ...

Page 14

... VCC_RXTTL RCLKN RBC1 RCLK RBC0 VSST GND_RXTTL VSST GND_RXTTL 14 PI90SD1636A SERDES Gigabit Ethernet Transceiver Comments Connect to the ground plane. 10-bit parallel data input pins. Connect to 3.3V Connect to 3.3V Connect to the ground plane. Connect to the ground plane. Pericom requires no external caps. External capacitor will not affect performance Pericom requires no external caps ...

Page 15

... VCC Connect to 3.3V VSSD GND Connect to the ground plane VDDD VCC Connect to 3.3V VDDP VCC_TXECL Connect to 3.3V TX- -DOUT High-speed serial data output TX+ +DOUT High-speed serial data output VDDP VCC_TXHS Connect to 3.3V VSSD GND_TXHS Connect to the ground plane 15 PI90SD1636A SERDES Gigabit Ethernet Transceiver Comments PS8641 10/14/04 ...

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