mk2069-04 Integrated Device Technology, mk2069-04 Datasheet

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mk2069-04

Manufacturer Part Number
mk2069-04
Description
Vcxo-based Universal Clock Translator
Manufacturer
Integrated Device Technology
Datasheet

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VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
Description
The MK2069-04 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that features a PLL
(Phase-Locked Loop) input reference divider and feedback
divider that have a wide numeric range selectable by the
user. This enables a complex PLL multiplication ratio that
can be used for translation between clock frequency
standards.
The on-chip VCXO produces a stable, low jitter output clock
using a phase detector frequency down to 8 kHz or lower.
This means the MK2069-04 can translate between clock
frequencies that have a low common denominator, such as
the 8 kHz frame clock common with telecom standards. The
MK2069-04 also provides jitter attenuation of the input
clock and can accept a low input frequency as well.
The device is optimized for user configurability by providing
access to all major PLL divider functions. No power-up
programming is needed as configuration is pin selected.
External VCXO loop filter components provide an additional
level of user configurability.
The MK2069-04 includes a lock detector (LD) output that
serves as a clock status monitor. The clear (CLR) input
enables rapid synchronization to the phase of a newly
selected input clock.
Block Diagram
IDT™ / ICS™ VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
C L R
IC L K
D iv id er
R P V
R P V
1 , 8
2 to 4 0 9 7
R V 1 1:0
D iv id e r
R V
12
IS E T
V C X O
P L L
D etector
P hase
L F
C harge
P um p
L F R
F V D iv id er
1 to 4 09 6
X 1
P u lla b le
V C X O
F V 1 1 :0
x ta l
12
X 2
1
1 ,2 ,1 2,1 6
L o c k D e te c to r
D iv id e r
S V 1 :0
Features
S V
Input clock frequency <1 kHz to 170 MHz
Output clock frequency of 500 kHz to 160 MHz
Clock translation examples:
Jitter attenuation of input clock provided by VCXO circuit.
Jitter transfer characteristics user configured through
external loop filter component selection.
Low jitter and phase noise generation.
PLL lock status output
PLL Clear function allows seamless synchronizing to an
altered input clock phase
2nd PLL provides frequency translation of VCXO PLL
output (VCLK) to a higher or alternate output frequency
(TCLK).
Device will free-run in the absence of an input clock
based on VCXO frequency.
56-pin TSSOP package
Single 3.3 V power supply
5 V tolerant clock input
Available in Pb (lead) free package
2
L D C
MHz)
T1 (1.544 MHz) to/from E1 (2.048 MHz)
T3 (44.736 MHz) to/from E3 (34.368 MHz)
OC-3 (155.52 MHz) to/from T1 (1.544 MHz)
CCIR-601 (27 MHz) to/from SMPTE 274M (74.125
T ran s la to r
P L L
L D R
2 to 1 6 , e v e n o n ly
F T D iv id e r
F T 2 :0
V C O
3
D ivid e r
2 , 1 6
S T
S T
MK2069-04
DATASHEET
MK2069-04
G N D
V D D
4
4
REV G 090905
V C L K
O E V
T C L K
O E T
R C L K
O E R
L D
O E L

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mk2069-04 Summary of contents

Page 1

... External VCXO loop filter components provide an additional level of user configurability. The MK2069-04 includes a lock detector (LD) output that serves as a clock status monitor. The clear (CLR) input enables rapid synchronization to the phase of a newly selected input clock. ...

Page 2

... VCXO AND SYNTHESIZER Divider Notes Ratio 2 RV Divide Value 3 = Address + 2 : 4097 Notes 2 For FV addresses 0 to 4094, FV Divide Value 3 = Address + 2 : 4096 1 SV Divider Ratio FT0 FT Divider Ratio MK2069-04 REV G 090905 ...

Page 3

... Ground connection for internal digital circuitry. Power Lock detector threshold setting circuit connection. Refer to circuit on page 10. — VCXO PLL phase detector Reference Clock output. Ground Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR). 3 VCXO AND SYNTHESIZER Pin Description MK2069-04 REV G 090905 ...

Page 4

... SV1 56 RPV Functional Description The MK2069- PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to an input reference clock. It contains two cascaded PLL’s with user selectable divider ratios. The first PLL is VCXO-based and uses an external pullable crystal as part of the normal “ ...

Page 5

... VCXO-BASED UNIVERSAL CLOCK TRANSLATOR IDT™ / ICS™ VCXO-BASED UNIVERSAL CLOCK TRANSLATOR Application Information The MK2069- mixed analog / digital integrated circuit that is sensitive to PCB (printed circuit board) layout and external component selection. Used properly, the device will provide the same high performance expected from a canned VCXO-based hybrid timing device, but at a lower cost ...

Page 6

... MK2069-04 Loop Response and JItter Attenuation Characteristics The MK2069-04 will reduce the transfer of phase jitter existing on the input reference clock to the output clock. This operation is known as jitter attenuation. The low-pass frequency response of the VCXO PLL loop is the mechanism that provides input jitter attenuation ...

Page 7

... VCXO AND SYNTHESIZER and ----- - = value that would be used for a damping factor use the filter P should be increased in value until it P MK2069-04 in the loop P P value that is too low is too P REV G 090905 ...

Page 8

... SET VCXO Gain ( increases CP 8 VCXO AND SYNTHESIZER 10E+6 Recommended Range of Operation ) vs. XTAL Frequency MK2069-04 REV G 090905 3 0 ...

Page 9

... When used in 9 VCXO AND SYNTHESIZER is equal to the input frequency divided PD should be typically at least PD Loop Loop Passband Note BW Damp. Peaking (-3dB) 4.0 0.15dB at 1Hz 1 1.4 1.2dB at 6Hz 2 4.5 0.12dB at 1Hz 0.85 1.8dB at 8Hz useful when S MK2069-04 , also needs to PD REV G 090905 ...

Page 10

... TCLK is always locked to VCLK regardless of the state of the CLR input. Lock Detection The MK2069-04 includes a lock detection feature that indicates lock status of VCLK relative to the selected input reference clock. When phase lock is achieved (such as following power-up), the LD output goes high. When phase ...

Page 11

... RLD and CLD components but the LD output will not be used, RLD can remain unstuffed and CLD can be replaced with a resistor (< 10 kohm). Power Supply Considerations As with any integrated clock device, the MK2069-04 has a special set of power supply requirements: • The feed from the system power supply must be filtered for noise that can cause output clock jitter ...

Page 12

... L and bulk decoupling capacitor may be mounted on the back). Other signal traces should be routed away from the MK2069-04. This includes signal traces on PCB traces just underneath the device layers adjacent to the ground plane layer used by the device. 6) Because each input selection pin includes an internal pull-up device, those inputs requiring a logic high state (“ ...

Page 13

... The crystal should be keep away from these clock sources. The ICS Applications Note MAN05 may also be referenced for additional suggestions on layout of the crystal section. IDT™ / ICS™ VCXO-BASED UNIVERSAL CLOCK TRANSLATOR 13 VCXO AND SYNTHESIZER MK2069-04 REV G 090905 ...

Page 14

... 603 MK2069 RLD G 38 603 37 CLD 36 603 External loop capacitor C (film type External loop resistor R S current value 33 Ω omitted. See text on page 10. MK2069- 603 RT 603 G REV G 090905 ...

Page 15

... LDR pin. Use RCLK as the scope trigger. LDR will produce a negative pulse equal in length to the charge pump pulse. 3.5) Filter leakage can also be caused by the use of improper loop capacitors. Refer to the section titled ‘Loop Filter Capacitor Type’ on page 9. 15 VCXO AND SYNTHESIZER /20 MK2069-04 REV G 090905 ...

Page 16

... VCXO-BASED UNIVERSAL CLOCK TRANSLATOR Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2069-04. These ratings, which are standard values for ICS industrial rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability ...

Page 17

... VDD, providing utility in hot-plug line card IH 17 VCXO AND SYNTHESIZER Min. Typ. Max. Units 3.15 3.3 3. VDD + V 0.4 -0.4 0.8 V 200 kΩ VDD/2+1 VDD + V 0.4 VDD/2+1 5.5 V -0.4 VDD/2-1 V µA -10 +10 µA -10 + VDD-0.4 V 2.4 V 0.4 V ±50 mA ± VDD V MK2069-04 REV G 090905 ...

Page 18

... VCXO AND SYNTHESIZER Min. Typ. Max. Units 13.5 27 MHz ±115 ±150 ppm -300 -150 ppm 0.008 170 MHz 0.002 160 MHz 10 nsec 0.001 27 MHz 0 320 MHz 105 0.5 VCLK Period MK2069-04 REV G 090905 ...

Page 19

... L t 2 Rising edges Rising edges Rising edges OUT 19 VCXO AND SYNTHESIZER Min. Typ. Max. Units 2 1.5 +10 ns Ω 20 MK2069-04 REV G 090905 ...

Page 20

... MK2069-04GI MK2069-04GITR MK2069-04GI MK2069-04GILF MK2069-04GILF MK2069-04GILFTR MK2069-04GILF Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...

Page 21

... MK2069-04 VCXO-BASED UNIVERSAL CLOCK TRANSLATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...

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