mc145428 Lansdale Semiconductor, Inc., mc145428 Datasheet

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mc145428

Manufacturer Part Number
mc145428
Description
Asynchronous-to-synchronous And Synchronous-to-asynchronous Converter
Manufacturer
Lansdale Semiconductor, Inc.
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
mc145428P
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Legacy Device: Motorola MC145428
and synchronous-to-asynchronous data conversion. It is ideally suited for
voice/data digital telesets supplying an EIA-232 compatible data port into a
synchronous transmission link. Other applications include: data multiplexers,
concentrators, data-only switching, and PBX-based local area networks. This
low-power CMOS device directly interfaces with either the 64 kbps or 8kbps
channel of Motorola’s MC145422 and MC145426 Universal Digital Loop
Transceivers (UDLTs), as well as the MC145421 and MC145425 Second
Generation Universal Digital Loop Transceivers (UDLT II).
Page 1 of 14
BR1-BR3
The ML145428 Data Set Interface provides asynchronous-to-synchronous
• Provides the Interface Between Asynchronous Data Ports and
• Up to 128 kbps Asynchronous Data Rate Operation
• Up to 2.1 Mbps Synchronous Data Rate Operation
• On-Board Bit Rate Clock Generator with Pin Selectable Bit Rates of
• Accepts Asynchronous Data Words of 8 or 9 Bits in Length
• False Start Detection Provided
• Automatic Sync Insertion and Checking
• Single 5 V Power Supply
• Low Power Consumption of 5 mW Typical
• Application Notes AN943 and AN946
• Operating Temperature Range T A = –40º to +85ºC.
BRCLK
BCLK
Synchronous Transmission Lines
300, 1200, 1400, 4800, 9600, 19200 and 38400 bps or an Externally
Supplied 16 Times Bit Rate Clock
RxD
RxS
TxS
TxD
SB
DL
STRIPPER
BAUD
RATE
GEN
FORMATTER
DATA
DATA
BLOCK DIAGRAM
FIFO
FIFO
Rx
Tx
CONTROL
SYNCHRONOUS
SYNCHRONOUS
TRANSMITTER
RECEIVER
CHANNEL
CHANNEL
www.lansdale.com
ML145428
Asynchronous–to–Synchronous
and Synchronous–to–
Asynchronous Converter
DCO
DOE
DIE
DCLK
CM
RESET
DCI
CROSS REFERENCE/ORDERING INFORMATION
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PACKAGE
P DIP 20
SOG 20
20
20
1
BRCLK
BCLK 5
TxD
BR1
BR2
BR3
TxS
V
1
DL
SB
SS
PIN ASSIGNMENT
MC145428DW
MOTOROLA
MC145428P
1
2
3
4
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
P DIP 20 = RP
SOG 20 = -6P
CASE 751D
CASE 732
PLASTIC
PLASTIC
V
RESET
DCO
DOE
CM
DCLK
DIE
DCI
RxS
RxD
ML145428-6P
ML145428RP
DD
LANSDALE
Issue 0

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mc145428 Summary of contents

Page 1

... Legacy Device: Motorola MC145428 The ML145428 Data Set Interface provides asynchronous-to-synchronous and synchronous-to-asynchronous data conversion ideally suited for voice/data digital telesets supplying an EIA-232 compatible data port into a synchronous transmission link. Other applications include: data multiplexers, concentrators, data-only switching, and PBX-based local area networks. This low-power CMOS device directly interfaces with either the 64 kbps or 8kbps channel of Motorola’ ...

Page 2

... DSI’s DATA FORMATTER to re–create data bits between the start and stop bits when outputting data at its RxD asynchronous output. A high on this pin selects a 9 bit data word, a low selects an 8 bit data word length. www.lansdale.com LANSDALE Semiconductor, Inc. Issue 0 ...

Page 3

... DCI pin to the Rx FIFO until one “flag” word is input at the DCI pin. (Also see RxS pin description) DCI, DATA CHANNEL INPUT Synchronous data is input on this pin on the falling edges of DC when DIE is high. www.lansdale.com LANSDALE Semiconductor, Inc. Issue 0 ...

Page 4

... ML145428 Page www.lansdale.com LANSDALE Semiconductor, Inc. Issue 0 ...

Page 5

... ML145428 Page www.lansdale.com LANSDALE Semiconductor, Inc. Issue 0 ...

Page 6

... FIFO for transmission, the synchronous data transmitter sends a special synchronizing flag pattern (011111110). When a break condition is detected by the data stripper and no data is available at the top of the Tx FIFO, the break pattern (111111110) is sent. Figure 2A depicts this operation. www.lansdale.com LANSDALE Semiconductor, Inc. Issue 0 ...

Page 7

... Tx FIFO. Note that the TxS line will immediately go high after RESET goes high, while RxS will remain low until framing is detected. The synchronous channel www.lansdale.com LANSDALE Semiconductor, Inc. Issue 0 ...

Page 8

... DC clock (i.e., when the DC clock is high). The following table summarizes when data bits are advanced from the synchronous channel transmitter and when data bits are read by the synchronous channel receiver dependent on the CM control line. (Shown below in Table 2.) www.lansdale.com LANSDALE Semiconductor, Inc. Issue 0 ...

Page 9

... ML145428 Page www.lansdale.com LANSDALE Semiconductor, Inc. Issue 0 ...

Page 10

... ML145428 Page www.lansdale.com LANSDALE Semiconductor, Inc. Issue 0 ...

Page 11

... ML145428 Page www.lansdale.com LANSDALE Semiconductor, Inc. Issue 0 ...

Page 12

... ML145428 Page www.lansdale.com LANSDALE Semiconductor, Inc. Issue 0 ...

Page 13

... ML145428 Page www.lansdale.com LANSDALE Semiconductor, Inc. Issue 0 ...

Page 14

... Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the cus- tomer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc. Page ...

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