mc145201dt Freescale Semiconductor, Inc, mc145201dt Datasheet

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mc145201dt

Manufacturer Part Number
mc145201dt
Description
2.0 Ghz Pll Frequency Synthesizers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC145201DT.pdf (23 pages)
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
2.0 GHz PLL Frequency
Synthesizers
Include On–Board 64/65 Prescalers
interfaces capable of direct usage up to 2.0 GHz. A special architecture makes
these PLLs very easy to program because a byte–oriented format is utilized.
Due to the patented BitGrabber
required for random access of the three registers. Thus, tuning can be
accomplished via a 3–byte serial transfer to the 24–bit A register. The interface
is both SPI and MICROWIRE compatible.
output and a double–ended phase detector output. Both phase detectors have
linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor tied
from the Rx pin to ground. This current can be varied via the serial port.
frequency detectors; the detector supply may range up to 9.5 V. The MC145201
has lower–voltage phase/frequency detectors optimized for single–supply
systems of 5 V 10%.
single–ended mode. Also featured are on–board support of an external crystal
and a programmable reference output. The R, A, and N counters are fully
programmable. The C register (configuration register) allows the parts to be
configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
loaded into the counters, on–board circuitry synchronizes the update of the A
register if the A or N counters are loading. Similarly, an update of the R register
is synchronized if the R counter is loading.
the three counters (R, A, and N) simultaneously.
BitGrabber is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
REV 4
1/98
MOTOROLA
The MC145200 and MC145201 are single–package synthesizers with serial
Each device features a single–ended current source/sink phase detector
The MC145200 features logic–level converters and high–voltage phase/
Each part includes a differential RF input which may be operated in a
In order to have consistent lock times and prevent erroneous data from being
The double–buffered R register allows new divide ratios to be presented to
Motorola, Inc. 1998
Maximum Operating Frequency: 2000 MHz @ V in = 200 mV p–p
Operating Supply Current: 12 mA Nominal
Operating Supply Voltage Range (V DD and V CC Pins): 4.5 to 5.5 V
Operating Supply Voltage Range of Phase Detectors (V PD Pin) —
Current Source/Sink Phase Detector Output Capability: 2 mA Maximum
Gain of Current Source/Sink Phase/Frequency Detector Controllable via
Serial Port
Operating Temperature Range: – 40 to + 85 C
R Counter Division Range: (1 and) 5 to 8191
Dual–Modulus Capability Provides Total Division up to 262,143
High–Speed Serial Interface: 4 Mbps
OUTPUT A Pin, When Configured as Data Out, Permits Cascading of Devices
Two General–Purpose Digital Outputs — OUTPUT A: Totem–Pole (Push–Pull)
Power–Saving Standby Feature with Orderly Recovery for Minimizing Lock
Times, Standby Current: 30 A
Evaluation Kit Available (Part Numbers MC145200EVK and MC145201EVK)
See Application Note AN1253/D for Low–Pass Filter Design, and
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping
MC145200: 8.0 to 9.5 V
MC145201: 4.5 to 5.5 V
TN98012300
registers, no address/steering bits are
OUTPUT B: Open–Drain
20
20
MC145200F
MC145201F
MC145200DT
MC145201DT
REF out
TEST 1
ORDERING INFORMATION
PD out
MC145200
MC145201
GND
V PD
LD
Rx
f in
R
V
PIN ASSIGNMENT
1
1
1
2
3
4
5
6
7
8
9
10
MC145200 MC145201
SOG Package
SOG Package
TSSOP
TSSOP
Order this document
20
19
18
17
16
15
14
13
12
11
SOG PACKAGE
CASE 751J
by MC145200/D
CASE 948D
F SUFFIX
DT SUFFIX
REF in
D in
CLK
ENB
OUTPUT A
OUTPUT B
V DD
TEST 2
V CC
f in
TSSOP
1

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mc145201dt Summary of contents

Page 1

... Order this document by MC145200/D MC145200 MC145201 F SUFFIX SOG PACKAGE 20 CASE 751J 1 DT SUFFIX TSSOP 20 CASE 948D 1 ORDERING INFORMATION MC145200F SOG Package MC145201F SOG Package MC145200DT TSSOP MC145201DT TSSOP PIN ASSIGNMENT REF out 1 20 REF CLK ENB 5 16 ...

Page 2

REF in OSC OR 4–STAGE DIVIDER 1 (CONFIGURABLE) REF out 18 CLK SHIFT REGISTER 19 AND D in CONTROL 24 LOGIC 17 ENB INTERNAL CONTROL INPUT 10 AMP f in SUPPLY CONNECTIONS: PIN 12 = ...

Page 3

ELECTRICAL CHARACTERISTICS ( 4.5 to 5.5 V, Voltages Referenced to GND – unless otherwise stated; MC145200 8.0 to 9.5 V; MC145201 ...

Page 4

ANALOG CHARACTERISTICS—CURRENT SOURCE/SINK OUTPUT—PD out (I out 2 mA 4 Parameter Maximum Source Current Variation Maximum Sink–vs–Source Mismatch (Note 3) Output Voltage Range (Note 3) NOTES: 1. Percentages calculated ...

Page 5

CLK 50% 10 1/f clk t PLH t PHL 90% OUTPUT A 50% (DATA OUT) 10% t TLH t THL Figure 1. VALID 50 50% ...

Page 6

LOOP SPECIFICATIONS ( 4.5 to 5.5 V unless otherwise indicated – Symbol Parameter V in Input Voltage Range ref Input ...

Page 7

OUTPUT 10% t THL Figure 11. Switching Waveform NORMALIZED INPUT IMPEDANCE — SERIES FORMAT ( (PIN 11) SOG PACKAGE Frequency Marker MOTOROLA DEVICE UNDER TEST ...

Page 8

PIN DESCRIPTIONS DIGITAL INTERFACE PINS D in Serial Data Input (Pin 19) The bit stream begins with the most significant bit (MSB) and is shifted in on the low–to–high transition of CLK. The bit pattern is 1 byte (8 bits) ...

Page 9

If A23 = high and A22 = low, OUTPUT A is configured This signal is the buffered output of the 12–stage N counter. The f V signal appears as normally low and pulses high, and can ...

Page 10

Frequency and Phase essentially a floating state; voltage at pin determined by loop filter This output can be enabled, disabled, and inverted via the C register. If desired, PD out can be forced ...

Page 11

V PD Positive Power Supply (Pin 5) This pin supplies power to both phase/frequency detectors A and B. The voltage applied on this pin must be no less than the potential applied to the V DD pin. The maximum voltage ...

Page 12

Nominal MC145200 PD out Source Current vs Rx Resistance 100 ...

Page 13

ENB CLK MSB this point, the new byte is transferred to the C register and stored. No other registers are affected. C7 — POL: Selects the output polarity of the phase/frequency detectors. When set high, ...

Page 14

Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç ...

Page 15

ENB CLK MSB R15 R14 R13 R12 R11 CRYSTAL MODE, SHUT DOWN 1 CRYSTAL MODE, ACTIVE 2 REFERENCE MODE, REF in ENABLED and REF out STATIC LOW 3 REFERENCE MODE, REF out ...

Page 16

R REFERENCE REF FEEDBACK out High voltage level Low voltage level *At this point, when both f R and ...

Page 17

Power is dissipated in the effective series resistance of the crystal Figure 21. The maximum drive level specified by the crystal manufacturer represents the maximum stress that the crystal can withstand without damage or excessive shift ...

Page 18

PHASE–LOCKED LOOP — LOW–PASS FILTER DESIGN (A) PD out VCO R C NOTE: For (A), using K in amps per radian with the filter’s impedance transfer function, Z(s), maintains units of volts per radian for the detector/ filter combination. Additional ...

Page 19

THRESHOLD DETECTOR INTEGRATOR OPTIONAL LOOP ERROR SIGNALS (NOTE 1) LOW–PASS FILTER NOTES: 1. When used, the R and V outputs are fed to an external combiner/loop filter. See the Phase– Locked Loop — Low–Pass Filter Design page for additional information. ...

Page 20

Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç ...

Page 21

Figure 26. Accessing the R Registers of Two Cascaded Devices MOTOROLA Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç ...

Page 22

SOG (SMALL OUTLINE GULL–WING) PACKAGE - 0.13 (0.005 0.13 (0.005 TSSOP (THIN SHRUNK SMALL OUTLINE PACKAGE PIN ...

Page 23

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...

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