mc14069ubdtr2 ON Semiconductor, mc14069ubdtr2 Datasheet

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mc14069ubdtr2

Manufacturer Part Number
mc14069ubdtr2
Description
Hex Inverter
Manufacturer
ON Semiconductor
Datasheet

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MC14069UB
Hex Inverter
and N−channel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
Features
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
(e.g., either V
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 8
Symbol
V
I
The MC14069UB hex inverter is constructed with MOS P−channel
in
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level
Schottky TTL Load Over the Rated Temperature Range
in
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Triple Diode Protection on All Inputs
Pin−for−Pin Replacement for CD4069UB
Meets JEDEC UB Specifications
Pb−Free Packages are Available
V
T
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
P
, V
, I
T
T
stg
DD
A
D
L
out
out
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
SS
SS
or V
v (V
DD
in
). Unused outputs must be left open.
Parameter
or V
(Voltages Referenced to V
out
) v V
DD
.
in
and V
−0.5 to V
SS
−0.5 to +18.0
−55 to +125
−65 to +150
out
)
Value
± 10
500
260
should be constrained
DD
+ 0.5
1
Unit
mW
mA
°C
°C
°C
V
V
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
(Note: Microdot may be in either location)
ORDERING INFORMATION
A
WL, L
YY, Y
WW, W
G or G
http://onsemi.com
CASE 948G
CASE 751A
SOEIAJ−14
TSSOP−14
DT SUFFIX
CASE 646
CASE 965
P SUFFIX
D SUFFIX
F SUFFIX
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PDIP−14
SOIC−14
Publication Order Number:
14
1
14
14
1
1
MC14069UBCP
DIAGRAMS
AWLYYWWG
14
MC14069UB
MC14069UB/D
MARKING
1
AWLYWW
ALYWG
14069UG
ALYWG
069U
14
G
G

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mc14069ubdtr2 Summary of contents

Page 1

MC14069UB Hex Inverter The MC14069UB hex inverter is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These inverters find primary use where low power dissipation and/or high noise immunity is desired. Each of the ...

Page 2

... ORDERING INFORMATION Device MC14069UBCP MC14069UBCPG MC14069UBD MC14069UBDG MC14069UBDR2 MC14069UBDR2G MC14069UBDTR2 MC14069UBDTR2G MC14069UBFEL MC14069UBFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free ...

Page 3

ELECTRICAL CHARACTERISTICS Î Î Î Î Î ...

Page 4

−T− SEATING PLANE 0.13 (0.005) PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE http://onsemi.com 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI ...

Page 5

... K D SEATING 14 PL PLANE 0.25 (0.010 14X 0.58 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOIC−14 CASE 751A−03 ISSUE 0.25 (0.010 ...

Page 6

... S A −V− C 0.10 (0.004) −T− SEATING G D PLANE 14X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE ...

Page 7

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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