74lvc3g04dp NXP Semiconductors, 74lvc3g04dp Datasheet

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74lvc3g04dp

Manufacturer Part Number
74lvc3g04dp
Description
Triple Inverter
Manufacturer
NXP Semiconductors
Datasheet

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Part Number
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Part Number:
74LVC3G04DP
Manufacturer:
ROHM
Quantity:
842
Part Number:
74LVC3G04DP
Manufacturer:
NXP/恩智浦
Quantity:
20 000
1. General description
2. Features
The 74LVC3G04 provides three inverting buffers.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
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I
I
I
I
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74LVC3G04
Triple inverter
Rev. 05 — 5 October 2007
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
ESD protection:
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
N
N
N
N
N
24 mA output drive (V
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CC
= 3.0 V)
Product data sheet
OFF
. The I
OFF

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74lvc3g04dp Summary of contents

Page 1

Triple inverter Rev. 05 — 5 October 2007 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3 devices. This feature allows the use of these devices as translators ...

Page 2

... Table 1. Ordering information Type number Package Temperature range 74LVC3G04DP +125 C 74LVC3G04DC +125 C 74LVC3G04GT +125 C 74LVC3G04GM +125 C 4. Marking Table 2. Marking Type number 74LVC3G04DP 74LVC3G04DC 74LVC3G04GT 74LVC3G04GM 5. Functional diagram mna720 Fig 1. Logic symbol ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 74LVC3G04 GND 4 Transparent top view Fig 5. Pin configuration SOT833-1 (XSON8) 6.2 Pin description Table 3. Pin description Symbol ( Pin SOT505-2, SOT765-1 and SOT833-1 ...

Page 4

... NXP Semiconductors 7. Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current ...

Page 5

... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter +85 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current ...

Page 6

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF I supply current CC I additional supply current CC [1] All typical values are measured ...

Page 7

... NXP Semiconductors C = output load capacitance in pF supply voltage number of inputs switching sum of outputs 12. Waveforms Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 7. The input (nA) to output (nY) propagation delays Table 9 ...

Page 8

... NXP Semiconductors Test data is given in Table 10. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 8. Load circuitry for switching times Table 10 ...

Page 9

... NXP Semiconductors 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

Page 10

... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 11

... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 12

... NXP Semiconductors XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 0.15 1.55 OUTLINE VERSION IEC SOT902 Fig 12 ...

Page 13

... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date 74LVC3G04_5 20071005 • Modifications: In current ...

Page 14

... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

Page 15

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 Abbreviations ...

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