pcf85162 NXP Semiconductors, pcf85162 Datasheet
pcf85162
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pcf85162 Summary of contents
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... Universal LCD driver for low multiplex rates Rev. 01 — 7 January 2010 1. General description The PCF85162 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) multiplexed LCD containing up to four backplanes and segments. It can be cascaded for larger LCD applications. The PCF85162 is compatible with most ...
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... AND TIMING SYNC OSC OSCILLATOR V DD SCL INPUT FILTERS SDA Fig 1. Block diagram of PCF85162 PCF85162_1 Product data sheet Universal LCD driver for low multiplex rates Ordering information Package Name Description TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm Marking codes ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Top view. For mechanical details, see Fig 2. Pinning diagram for PCF85162T PCF85162_1 Product data sheet Universal LCD driver for low multiplex rates S23 1 S24 2 3 S25 4 S26 S27 5 S28 6 S29 7 S30 8 9 S31 10 SDA SCL 11 SYNC ...
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... I C-bus address input 20 ground supply voltage 21 LCD supply voltage LCD backplane outputs 26 to 48, LCD segment outputs Rev. 01 — 7 January 2010 PCF85162 © NXP B.V. 2010. All rights reserved ...
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... LCDs. It can directly drive static or multiplexed LCD containing up to four backplanes and segments. The possible display configurations of the PCF85162 depend on the number of active backplane outputs required. A selection of display configurations is shown in of these configurations can be implemented in the typical system shown in Table 4 ...
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... LCD is calculated with on(RMS ----------------------------- - V LCD 2 × Rev. 01 — 7 January 2010 PCF85162 and V . The center resistor is LCD off RMS on RMS ------------------------ - ----------------------- - LCD LCD ∞ 0.354 0.791 2.236 0.333 0.745 2.236 ...
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... LCD when = ( ) LCD off RMS is sometimes referred as the LCD operating voltage. LCD Rev. 01 — 7 January 2010 PCF85162 Equation and is determined from Equation = 2.449V ( ) ( ) off RMS off RMS ) 3 = 2.309V ( ) off RMS ⁄ 1 bias is used. 3 © NXP B.V. 2010. All rights reserved. ...
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... LCD (b) Resultant waveforms at LCD segment. (t) − (t). state1 Sn BP0 = V . on(RMS) LCD (t) − (t). state2 ( BP0 = 0 V. off(RMS) Rev. 01 — 7 January 2010 PCF85162 Figure 4. fr LCD segments state 1 state 2 (on) (off) 013aaa207 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF85162 allows the use of Figure Fig 5. Waveforms for the 1:2 multiplex drive mode with PCF85162_1 Product data sheet Universal LCD driver for low multiplex rates ⁄ ...
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... LCD (b) Resultant waveforms (t) − (t). state1 Sn BP0 = 0.745V . on(RMS) LCD (t) − (t). state2 Sn BP1 = 0.333V . off(RMS) LCD Rev. 01 — 7 January 2010 PCF85162 T fr LCD segments state 1 state 2 013aaa209 at LCD segment. ⁄ 1 bias 3 © NXP B.V. 2010. All rights reserved ...
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... LCD (b) Resultant waveforms at LCD segment. (t) − (t). state1 Sn BP0 = 0.638V . on(RMS) LCD (t) − (t). state2 Sn BP1 = 0.333V . off(RMS) LCD Rev. 01 — 7 January 2010 PCF85162 T fr LCD segments state 1 state 2 013aaa210 ⁄ 1 bias 3 © NXP B.V. 2010. All rights reserved ...
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... LCD (b) Resultant waveforms at LCD segment. (t) − (t). state1 Sn BP0 = 0.577V . on(RMS) LCD (t) − (t). state2 Sn BP1 = 0.333V . off(RMS) LCD Rev. 01 — 7 January 2010 PCF85162 T fr LCD segments state 1 state 2 013aaa211 ⁄ 1 bias 3 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 7.5 Oscillator 7.5.1 Internal clock The internal logic of the PCF85162 and its LCD drive signals are timed either by its internal oscillator external clock. The internal oscillator is enabled by connecting pin OSC to pin V as the clock signal for several PCF85162 in the system that are connected in cascade. ...
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... Fig 9. Display RAM bit map When display data is transmitted to the PCF85162, the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triples, or quadruples ...
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LCD segments LCD backplanes S a n+2 b BP0 n+3 n+1 static n+5 n n+6 ...
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... The subaddress counter is also incremented when the data pointer overflows. In cascaded applications each PCF85162 in the cascade must be addressed separately. Initially, the first PCF85162 is selected by sending the device-select command matching the first device's hardware subaddress. Then the data pointer is set to the preferred display RAM address by sending the load-data-pointer command ...
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... Next the load-data-pointer command is sent to select the preferred display RAM address of the second PCF85162. This last step is very important because during writing data to the first PCF85162, the data pointer of the second PCF85162 is incremented. In addition, the hardware subaddress should not be changed whilst the device is being accessed on the I 7 ...
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... C-bus Figure SDA SCL data line stable; data valid Rev. 01 — 7 January 2010 PCF85162 Typ Max f = 1970 2640 Hz clk clk 2.57 3.44 1.28 1.72 0.64 0.86 ). For the range of the oscillator frequency clk Table 10). 11). change of data allowed mba607 © ...
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... Product data sheet Universal LCD driver for low multiplex rates Figure 12). S START condition MASTER SLAVE SLAVE TRANSMITTER/ RECEIVER RECEIVER RECEIVER 2 C-bus is illustrated in Rev. 01 — 7 January 2010 PCF85162 SDA SCL P STOP condition mbc622 Figure 13). MASTER MASTER TRANSMITTER/ TRANSMITTER RECEIVER mga807 Figure 14. ...
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... Bit The PCF85162 is a write-only device and will not respond to a read access, therefore bit 0 should always be logic 0. Bit 1 of the slave address byte, that a PCF85162 will respond to, is defined by the level tied to its SA0 input (V Having two reserved slave addresses allows the following on the same I • ...
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... The I C-bus protocol is shown in condition (S) from the I slave addresses available. All PCF85162 whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I ignored by all PCF85162 whose SA0 inputs are set to the alternative level. Fig 15. I After an acknowledgement, one or more command bytes follow, that define the status of each addressed PCF85162 ...
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... NXP Semiconductors 7.17 Command decoder The command decoder identifies command bytes that arrive on the I The commands available to the PCF85162 are defined in Table 8. Bit position labeled not used. Command Bit mode-set load-data-pointer device-select bank-select blink-select All available commands carry a continuation bit C in their most significant bit position as ...
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... RAM bank blinking BF[1:0] blink frequency selection 00 off Rev. 01 — 7 January 2010 PCF85162 [1] 1:2 multiplex RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 [1] [2] © NXP B.V. 2010. All rights reserved ...
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... V DD OSC SYNC A0, A1 LCD BP0, BP1, BP2, BP3 LCD S0 to S31 V SS Rev. 01 — 7 January 2010 PCF85162 SCL V SS SDA LCD V SS 001aac269 © NXP B.V. 2010. All rights reserved ...
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... CLK, SDA, SCL, SYNC, SA0, OSC each of the pins S0 to S31, BP0 to BP3 HBM CDM Ref. 7 “JESD78” Rev. 01 — 7 January 2010 PCF85162 ) is off, or vice versa. This may cause unwanted DD and V must be applied or removed together. LCD DD Min Max − ...
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... BP0 - BP3 and S0 - S31 LCD on pins BP0 to BP3 on pins S0 to S31 external clock with 50 % duty factor and when tested may therefore be driven to the V DD Rev. 01 — 7 January 2010 PCF85162 ° C; unless otherwise specified. Min Typ Max 1.8 - 5.5 [1] 2.5 - 6.5 [2] ...
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... Universal LCD driver for low multiplex rates − ° +85 amb Conditions [1] [ LCD = 400 kHz SCL f < 125 kHz SCL 2 on the I C-bus Rev. 01 — 7 January 2010 PCF85162 ° C; unless otherwise specified. Min Typ Max 1440 1970 2640 960 - 2640 ...
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... Universal LCD driver for low multiplex rates 1/f CLK t CLKH CLK t PD(SYNC BUF LOW t HD;STA SU;STA 2 C-bus timing waveforms Rev. 01 — 7 January 2010 PCF85162 t CLKL t PD(SYNC) t SYNCL t PD(LCD HD;DAT t SU;DAT HIGH © NXP B.V. 2010. All rights reserved. 0.7V DD 0.3V DD ...
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... A PCF85162 is configured as a clock master by connecting pin OSC to V Section 7.5.1). In this case the internal oscillator of the PCF85162 is generating the clock signal which is output on pin CLK. The other way round a PCF85162 is configured as clock slave by connecting pin OSC to V (see Section DD CLK ...
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... Is slave (OSC connected to V Fig 20. Cascaded PCF85162 configuration The SYNC line of all PCF85162 in the cascade must be connected to maintain the correct synchronization between all cascaded PCF85162. Synchronization is guaranteed after a Power-On Reset (POR). The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e ...
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... NXP Semiconductors Fig 21. Synchronization of the cascade for the various PCF85162 drive modes PCF85162_1 Product data sheet Universal LCD driver for low multiplex rates BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode ...
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... 2 scale (1) ( 0.28 0.2 0.2 12.6 6.2 8.3 0.5 0.17 0.1 0.1 12.4 6.0 7.9 REFERENCES JEDEC JEITA MO-153 Rev. 01 — 7 January 2010 PCF85162 θ detail 0.8 0.50 0.8 1 0.25 0.08 0.1 0.4 0.35 0.4 EUROPEAN ISSUE DATE PROJECTION 99-12-27 03-02-19 © NXP B.V. 2010. All rights reserved. ...
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... The moisture sensitivity level of the packages • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering PCF85162_1 Product data sheet Universal LCD driver for low multiplex rates Rev. 01 — 7 January 2010 PCF85162 © NXP B.V. 2010. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 23. Rev. 01 — 7 January 2010 PCF85162 Figure 23) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © NXP B.V. 2010. All rights reserved. ...
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... Liquid Crystal Display Least Significant Bit Most Significant Bit Moisture Sensitivity Level Printed-Circuit Board Random Access Memory Resistor Capacitor Root Mean Square Surface Mount Device Rev. 01 — 7 January 2010 PCF85162 peak temperature time 001aac844 © NXP B.V. 2010. All rights reserved ...
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... NX3-00092 — NXP store and transport requirements [10] SNV-FA-01-02 — Marking Formats Integrated Circuits [11] UM10204 — I PCF85162_1 Product data sheet Universal LCD driver for low multiplex rates 2 C-bus specification and user manual Rev. 01 — 7 January 2010 PCF85162 © NXP B.V. 2010. All rights reserved ...
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... Revision history Table 22. Revision history Document ID Release date PCF85162_1 20100107 PCF85162_1 Product data sheet Universal LCD driver for low multiplex rates Data sheet status Change notice Product data sheet - Rev. 01 — 7 January 2010 PCF85162 Supersedes - © NXP B.V. 2010. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 7 January 2010 PCF85162 © NXP B.V. 2010. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: PCF85162_1 All rights reserved. Date of release: 7 January 2010 ...