pcf8814 NXP Semiconductors, pcf8814 Datasheet - Page 17

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pcf8814

Manufacturer Part Number
pcf8814
Description
Pcf8814 65 X 96 Pixels Matrix Lcd Driver
Manufacturer
NXP Semiconductors
Datasheet
Philips Semiconductors
9.2
The serial interface is also a 3-line bidirectional interface
for communication between the microcontroller and the
LCD driver chip. The three lines are SCE (chip enable),
SCLK (serial clock) and SDIN (serial data). The PCF8814
is connected to the SDA line of the microcontroller by two
pads, SDIN (data input) and SDO (data output), which are
connected together.
9.2.1
In the write mode of the interface the microcontroller writes
commands and data to the PCF8814. Each data packet
contains a control bit D/C and a transmission byte. If D/C
is LOW, the following byte is interpreted as a command
byte. The instruction set is given in Table 8. If D/C is HIGH,
the following byte is stored in the display data RAM. After
every data byte the address counter is incremented
automatically. Figure 17 shows the general format of the
write mode and the definition of the transmission byte.
Any instruction can be sent in any order to the PCF8814.
The MSB is transmitted first. The serial interface is
initialized when SCE is HIGH. In this state, SCLK clock
2003 Mar 13
handbook, full pagewidth
65
(1) A transmission byte may be a command or a data byte.
3-line serial interface
W
96 pixels matrix LCD driver
RITE MODE
D/C
D/C
MSB
D7
transmission byte
D6
D5
transmission byte
D4
Fig.17 Serial data stream, write mode.
D3
D/C
D2
(1)
D1
transmission byte
LSB
D0
17
pulses have no effect and no power is consumed by the
serial interface. A falling edge on SCE enables the serial
interface and indicates the start of data transmission.
Figures 18, 19 and 20 show the protocol of the write mode:
When SCE is HIGH, SCLK clocks are ignored. During
the HIGH time of SCE the serial interface is initialized
At the falling SCE edge SCLK must be LOW (see
Fig.42)
SDIN is sampled at the rising edge of SCLK
D/C indicates whether the byte is a command (D/C = 0)
or RAM data (D/C = 1). It is sampled with the first rising
SCLK edge
If SCE stays LOW after the last bit of a command/data
byte, the serial interface expects the D/C bit of the next
byte at the next rising edge of SCLK (see Fig.19)
A reset pulse with RES interrupts the transmission. The
data being written into the RAM may be corrupted. The
registers are cleared. If SCE is LOW after the rising
edge of RES, the serial interface is ready to receive the
D/C bit of a command/data byte (see Fig.20).
D/C
transmission byte
Objective specification
MGW713
PCF8814

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