pcf8814 NXP Semiconductors, pcf8814 Datasheet - Page 30

• Manufacturer Part Number: pcf8814
• Description: Pcf8814 65 X 96 Pixels Matrix Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 16 Partial display control
11.1
Immediately following power-on all internal registers, as
well the RAM content, are undefined and the device must
be reset.
Reset is accomplished by applying an external pulse
(active LOW) at the pad RES. When reset occurs within
the specified time, all internal registers are reset, however
the RAM is still undefined. The state of the device after
reset is described in Section 11.2. The RES input must be
maximum time t
A reset can also be achieved by sending a reset
command. This command can be used during normal
operation but not to initialize the chip after power-on.
11.2
After reset the LCD driver has the following state:
11.3
Power-down mode gives the following circuit status:
Power-down mode is active when the display is OFF
(DON = 0) and all the pixels ON (DAL = 1) is set.
2003 Mar 13
0.3V
After power-on, RAM data is undefined, the reset signal
does not change the content of the RAM
All LCD outputs at V
Internal oscillator is off
Power-down mode is active.
All LCD outputs at V
Bias generator and V
external V
Oscillator off (external clock possible)
RAM contents unchanged; RAM data can be written
V
65
LCD
P2
0
0
0
0
1
1
1
1
DD1
Initialization
Reset function
Power-down mode
discharged to V
when V
96 pixels matrix LCD driver
LCD
P1
VHRL
0
0
1
1
0
0
1
1
can be disconnected
DD1
after V
reaches V
SS
SS
LCD
SS
(display off)
(display off)
in this mode.
P0
generator switched off;
0
1
0
1
0
1
0
1
DD1
DD(min)
going HIGH (see Fig.41).
MUX RATE
(or higher) within a
1 : 65
1 : 56
1 : 48
1 : 40
1 : 32
1 : 24
1 : 16
1 : 8
p
4
4
4
4
2
2
2
2
30
11.4
The bits DON, DAL and E select the display mode (see
Table 11).
11.4.1
When MX = 0, the display RAM is written from left to right
(X = 0, is on the left side). When MX = 1, the display RAM
is written from right to left (X = 0, is on the right side).
MX has an impact on the way the RAM is written. If
horizontal mirroring of the display is desired, the RAM
must first be rewritten, after changing MX.
11.4.2
When MY = 1, the display is mirrored vertically.
A change of this bit has an immediate effect on the display.
11.5
Y[3:0] defines the Y address of the display RAM. All
undefined states in Table 17 are reserved.
Table 17 X/Y address range
11.6
The X address points to the columns. The range of X is
from 0 to 95.
Y3
0
0
0
0
0
0
0
0
1
Display control
Set Y address of RAM
Set X address of RAM
M
M
IRROR
IRROR
Y2
0
0
0
0
1
1
1
1
0
X
Y
Y1
0
0
1
1
0
0
1
1
0
Objective specification
Y0
0
1
0
1
0
1
0
1
0
PCF8814
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
BANK