pcf8814 NXP Semiconductors, pcf8814 Datasheet - Page 54

• Manufacturer Part Number: pcf8814
• Description: Pcf8814 65 X 96 Pixels Matrix Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
17.4
The OTP circuitry in the PCF8814 contains many bits of
data. The circuitry for 1 bit is called an OTP slice. Each
OTP slice consists of 2 main parts: the OTP cell (a
non-volatile memory cell) and the shift register cell (a
flip-flop). The OTP cells are only accessible through their
shift register cells: reading from and writing to the OTP
cells is performed with the shift register cells, but only the
shift register cells are visible to the rest of the circuit. The
basic OTP architecture is shown in Fig.52.
The OTP architecture allows the following operations:
The reading of data from the OTP cells is initiated by
writing to the DON register. The OTP cells will not in fact
be updated until the device leaves power-down and the
oscillator starts. The reading operation needs up to 5 ms
to complete.
The shifting of the data into the shift register is performed
in the special mode CALMM. The CALMM mode is entered
using the CALMM command. Once in the CALMM mode
the data is shifted into the shift register via the interface at
the rate of 1 bit per command. After transmitting the last bit
and exiting the CALMM mode the serial interface is again
in the normal mode and all other commands can be sent.
Care should be taken that all bits of data (or a multiple of
all bits) are transferred before exiting the CALMM mode,
otherwise the bits will be in the wrong positions.
In the shift register the value of the seal bit is, like the
others, always zero at reset. To make sure the security
feature works correctly, the CALMM command is disabled
until power-down has been left. Once a refresh is
completed, the seal bit value in the shift register is valid
and permission to enter CALMM mode can thus be
determined.
The bits are shifted into the shift register in a pre-defined
order which is shown in Table 31. For example, the seal bit
is the last bit to be loaded into the shift register.
2003 Mar 13
Reading data from the OTP cells. The content of the
non-volatile OTP cells is transferred to the shift register
where upon it may affect the PCF8814 operation.
Writing data to the OTP cells. First, all bits of data are
shifted into the shift register via the interface. Then the
content of the shift register is transferred to the OTP
cells (there are some limitations related to storing data
in these cells, see Section 17.7).
Checking calibration without writing to the OTP cells.
Shifting data into the shift register allows the effects on
the V
65
OTP architecture
LCD
96 pixels matrix LCD driver
voltage to be observed.
54
Table 31 OTP bit order.
POSITION
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
2
3
4
5
6
7
8
9
Factory defaults
MMVOPCAL[5]
MMVOPCAL[4]
MMVOPCAL[3]
MMVOPCAL[2]
MMVOPCAL[1]
MMVOPCAL[0]
OTP CELL
MMVPR[7]
MMVPR[6]
MMVPR[5]
MMVPR[4]
MMVPR[3]
MMVPR[2]
MMVPR[1]
MMVPR[0]
MMSLD[2]
MMSLD[1]
MMSLD[0]
MMSLC[2]
MMSLC[1]
MMSLC[0]
MMSLB[2]
MMSLB[1]
MMSLB[0]
MMSLA[2]
MMSLA[1]
MMSLA[0]
MMBS[2]
MMBS[1]
MMBS[0]
MMS[1]
MMS[0]
SEAL
Objective specification
FI
PCF8814